iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	xilinx: Add simulation model for DSP48 (Virtex 4).	Marcin Kościelnicki	2020-01-29	3	-0/+304
*	xilinx: Test our DSP48A/DSP48A1 simulation models.	Marcin Kościelnicki	2019-12-23	4	-4/+359
*	Add pattern detection support for DSP48E1 model, check against vendor	Eddie Hung	2019-09-18	2	-4/+59
*	DSP48E1 sim model: add SIMD tests	David Shah	2019-08-08	2	-2/+112
*	DSP48E1 model: test CE inputs	David Shah	2019-08-08	1	-2/+9
*	DSP48E1 sim model: fix seq tests and add preadder tests	David Shah	2019-08-08	2	-6/+91
*	DSP48E1 sim model: seq test working	David Shah	2019-08-08	2	-10/+47
*	DSP48E1 sim model: Comb, no pre-adder, mode working	David Shah	2019-08-08	1	-6/+10
*	[wip] sim model testing	David Shah	2019-08-08	3	-13/+75
*	[wip] sim model testing	David Shah	2019-08-08	2	-0/+311
*	Improved xilinx "bram1" test	Clifford Wolf	2015-04-09	1	-1/+2
*	Added support for initialized xilinx brams	Clifford Wolf	2015-04-06	5	-19/+90
*	Added Xilinx test case for initialized brams	Clifford Wolf	2015-04-06	4	-0/+80
*	Various cleanups in xilinx techlib	Clifford Wolf	2015-01-18	1	-0/+2
*	Refactoring of memory_bram and xilinx brams	Clifford Wolf	2015-01-18	1	-3/+7
*	Cleanups in xilinx bram descriptions	Clifford Wolf	2015-01-07	1	-4/+4
*	Xilinx RAMB36/RAMB18 memory_bram support complete	Clifford Wolf	2015-01-06	1	-1/+1
*	Towards Xilinx bram support	Clifford Wolf	2015-01-06	1	-10/+49
*	Towards Xilinx bram support	Clifford Wolf	2015-01-06	2	-1/+3
*	Towards Xilinx bram support	Clifford Wolf	2015-01-06	1	-11/+18
*	Towards Xilinx bram support	Clifford Wolf	2015-01-06	2	-4/+8
*	Towards Xilinx bram support	Clifford Wolf	2015-01-05	4	-0/+148