Towards Xilinx bram support

4 files changed, 148 insertions, 0 deletions

diff --git a/techlibs/xilinx/tests/.gitignore b/techlibs/xilinx/tests/.gitignore
new file mode 100644
index 000000000..bc2f8babf
--- /dev/null
+++ b/techlibs/xilinx/tests/.gitignore
@@ -0,0 +1,3 @@
+bram1_cmp
+bram1.mk
+bram1_[0-9]*/
diff --git a/techlibs/xilinx/tests/bram1.sh b/techlibs/xilinx/tests/bram1.sh
new file mode 100644
index 000000000..3a72cce48
--- /dev/null
+++ b/techlibs/xilinx/tests/bram1.sh
@@ -0,0 +1,48 @@
+#!/bin/bash
+
+echo "all: all_list" > bram1.mk
+all_list="all_list:"
+
+for transp in 0 1; do
+for abits in 1 2 4 8 10 16 20; do
+for dbits in 1 2 4 8 10 16 20 24 30 32 40 48 50 56 60 64 70 72 80; do
+	if [ $(( (1 << $abits) * $dbits )) -gt 1000000 ]; then continue; fi
+	if [ $(( (1 << $abits) * $dbits )) -gt 100 ]; then continue; fi
+	id=`printf "%d%02d%02d" $transp $abits $dbits`
+	echo "Creating bram1_$id.."
+	rm -rf bram1_$id
+	mkdir -p bram1_$id
+	cp bram1.v bram1_tb.v bram1_$id/
+	sed -i "/parameter/ s,ABITS *= *[0-9]*,ABITS = $abits," bram1_$id/*.v
+	sed -i "/parameter/ s,DBITS *= *[0-9]*,DBITS = $dbits," bram1_$id/*.v
+	sed -i "/parameter/ s,TRANSP *= *[0-9]*,TRANSP = $transp," bram1_$id/*.v
+	{
+		echo "set -e"
+		echo "../../../../yosys -q -lsynth.log -p 'synth_xilinx -top bram1; write_verilog synth.v' bram1.v"
+		echo "xvlog --work gold bram1_tb.v bram1.v > gold.txt"
+		echo "xvlog --work gate bram1_tb.v synth.v > gate.txt"
+		echo "xelab -R gold.bram1_tb >> gold.txt"
+		echo "mv testbench.vcd gold.vcd"
+		echo "xelab -L unisim -R gate.bram1_tb >> gate.txt"
+		echo "mv testbench.vcd gate.vcd"
+		echo "../bram1_cmp <( grep '#OUT#' gold.txt; ) <( grep '#OUT#' gate.txt; )"
+	} > bram1_$id/run.sh
+	{
+		echo "bram1_$id/ok:"
+		echo "	@cd bram1_$id && bash run.sh"
+		echo "	@echo -n '[$id]'"
+		echo "	@touch \$@"
+	} >> bram1.mk
+	all_list="$all_list bram1_$id/ok"
+done; done; done
+
+cc -o bram1_cmp ../../../tests/tools/cmp_tbdata.c
+echo "$all_list" >> bram1.mk
+
+echo "Testing..."
+${MAKE:-make} -f bram1.mk
+echo
+
+# echo "Cleaning up..."
+# rm -rf bram1_cmp bram1.mk bram1_[0-9]*/
+
diff --git a/techlibs/xilinx/tests/bram1.v b/techlibs/xilinx/tests/bram1.v
new file mode 100644
index 000000000..034cc18e9
--- /dev/null
+++ b/techlibs/xilinx/tests/bram1.v
@@ -0,0 +1,24 @@
+module bram1 #(
+	parameter ABITS = 8, DBITS = 8, TRANSP = 0
+) (
+	input clk,
+
+	input [ABITS-1:0] WR_ADDR,
+	input [DBITS-1:0] WR_DATA,
+	input WR_EN,
+
+	input [ABITS-1:0] RD_ADDR,
+	output [DBITS-1:0] RD_DATA
+);
+	reg [DBITS-1:0] memory [0:2**ABITS-1];
+	reg [ABITS-1:0] RD_ADDR_BUF;
+	reg [DBITS-1:0] RD_DATA_BUF;
+
+	always @(posedge clk) begin
+		if (WR_EN) memory[WR_ADDR] <= WR_DATA;
+		RD_ADDR_BUF <= RD_ADDR;
+		RD_DATA_BUF <= memory[RD_ADDR];
+	end
+
+	assign RD_DATA = TRANSP ? memory[RD_ADDR_BUF] : RD_DATA_BUF;
+endmodule
diff --git a/techlibs/xilinx/tests/bram1_tb.v b/techlibs/xilinx/tests/bram1_tb.v
new file mode 100644
index 000000000..98e6bafe6
--- /dev/null
+++ b/techlibs/xilinx/tests/bram1_tb.v
@@ -0,0 +1,73 @@
+module bram1_tb #(
+	parameter ABITS = 8, DBITS = 8, TRANSP = 0
+);
+	reg clk;
+	reg [ABITS-1:0] WR_ADDR;
+	reg [DBITS-1:0] WR_DATA;
+	reg WR_EN;
+	reg [ABITS-1:0] RD_ADDR;
+	wire [DBITS-1:0] RD_DATA;
+
+	bram1 #(
+		// .ABITS(ABITS),
+		// .DBITS(DBITS),
+		// .TRANSP(TRANSP)
+	) uut  (
+		.clk    (clk    ),
+		.WR_ADDR(WR_ADDR),
+		.WR_DATA(WR_DATA),
+		.WR_EN  (WR_EN  ),
+		.RD_ADDR(RD_ADDR),
+		.RD_DATA(RD_DATA)
+	);
+
+	function [31:0] getaddr(input [3:0] n);
+		begin
+			case (n)
+				0: getaddr = 0;
+				1: getaddr = 2**ABITS-1;
+				2: getaddr = 'b101 << (ABITS / 3);
+				3: getaddr = 'b101 << (2*ABITS / 3);
+				4: getaddr = 'b11011 << (ABITS / 4);
+				5: getaddr = 'b11011 << (2*ABITS / 4);
+				6: getaddr = 'b11011 << (3*ABITS / 4);
+				7: getaddr = 123456789;
+				default: getaddr = 1 << (2*n-16);
+			endcase
+		end
+	endfunction
+
+	reg [DBITS-1:0] memory [0:2**ABITS-1];
+	reg [DBITS-1:0] expected_rd;
+
+	integer i, j;
+	initial begin
+		$dumpfile("testbench.vcd");
+		$dumpvars(0, bram1_tb);
+		clk <= 0;
+		for (i = 0; i < 256; i = i+1) begin
+			WR_DATA <= i;
+			WR_ADDR <= getaddr(i[7:4]);
+			RD_ADDR <= getaddr(i[3:0]);
+			WR_EN <= ^i;
+
+			#1; clk <= 1;
+			#1; clk <= 0;
+
+			if (TRANSP) begin
+				if (WR_EN) memory[WR_ADDR] = WR_DATA;
+				expected_rd = memory[RD_ADDR];
+			end else begin
+				expected_rd = memory[RD_ADDR];
+				if (WR_EN) memory[WR_ADDR] = WR_DATA;
+			end
+
+			for (j = 0; j < DBITS; j = j+1) begin
+				if (expected_rd[j] === 1'bx)
+					expected_rd[j] = RD_DATA[j];
+			end
+
+			$display("#OUT# | WA=%x WD=%x WE=%x | RA=%x RD=%x | %s", WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd === RD_DATA ? "ok" : "ERROR");
+		end
+	end
+endmodule