iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Rename cells_map.v to prevent clash with ff_map.v	Eddie Hung	2019-05-03	1	-6/+8
*	Move neg-pol to pos-pol mapping from ff_map to cells_map.v	Eddie Hung	2019-04-28	1	-0/+8
*	Call shregmap twice -- once for variable, another for fixed	Eddie Hung	2019-04-05	1	-0/+3
*	techmap inside map_cells stage	Eddie Hung	2019-04-05	1	-1/+0
*	Use soft-logic, not LUT3 instantiation	Eddie Hung	2019-04-04	1	-4/+2
*	Cleanup comments	Eddie Hung	2019-04-04	1	-5/+4
*	Fine tune cells_map.v	Eddie Hung	2019-03-20	1	-19/+15
*	Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length	Eddie Hung	2019-03-19	1	-53/+20
*	Add support for variable length Xilinx SRL > 128	Eddie Hung	2019-03-19	1	-11/+67
*	Fix spacing	Eddie Hung	2019-03-19	1	-1/+1
*	Fix INIT for variable length SRs that have been bumped up one	Eddie Hung	2019-03-19	1	-1/+1
*	Only accept <128 for variable length, only if $shiftx exclusive	Eddie Hung	2019-03-16	1	-5/+1
*	Cleanup synth_xilinx	Eddie Hung	2019-03-15	1	-1/+1
*	Working	Eddie Hung	2019-03-15	1	-40/+69
*	Reverse bits in INIT parameter for Xilinx, since MSB is shifted first	Eddie Hung	2019-03-14	1	-16/+32
*	Merge remote-tracking branch 'origin/master' into xc7srl	Eddie Hung	2019-03-14	1	-86/+18
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\| *	Changes required for VPR place and route synth_xilinx.	Keith Rothman	2019-03-01	1	-85/+19
* \|	Fix cells_map for SRL	Eddie Hung	2019-03-14	1	-19/+17
* \|	Refactor $__SHREG__ in cells_map.v	Eddie Hung	2019-03-13	1	-32/+24
* \|	Fix SRL16/32 techmap off-by-one	Eddie Hung	2019-02-28	1	-18/+24
* \|	synth_xilinx to call shregmap with enable support	Eddie Hung	2019-02-28	1	-23/+28
* \|	synth_xilinx to use shregmap with -params too	Eddie Hung	2019-02-28	1	-21/+18
* \|	Add techmap rule for $__SHREG_DFF_P_ to SRL16/32	Eddie Hung	2019-02-28	1	-0/+71
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*	Improving vpr output support.	Tim 'mithro' Ansell	2018-04-18	1	-0/+2
*	Various cleanups in xilinx techlib	Clifford Wolf	2015-01-18	1	-0/+84