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| author | Tim 'mithro' Ansell <me@mith.ro> | 2018-04-18 16:48:05 -0700 |
|---|---|---|
| committer | Tim 'mithro' Ansell <me@mith.ro> | 2018-04-18 16:55:12 -0700 |
| commit | d6bdefd2e93ad25fd63103d4b76a5573debc6d03 (patch) | |
| tree | 544397a34a4262465eb12b350469a9f63c0b19aa /techlibs/xilinx/cells_map.v | |
| parent | ca39e493ba78e7a4eaf3f0876321f892cce20f65 (diff) | |
| download | yosys-d6bdefd2e93ad25fd63103d4b76a5573debc6d03.tar.gz yosys-d6bdefd2e93ad25fd63103d4b76a5573debc6d03.tar.bz2 yosys-d6bdefd2e93ad25fd63103d4b76a5573debc6d03.zip | |
Improving vpr output support.
* Support output BLIF for Xilinx architectures.
* Support using .names in BLIF for Xilinx architectures.
* Use the same `NO_LUT` define in both `synth_ice40` and
`synth_xilinx`.
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 8e5a83ce5..0771be0b9 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -15,6 +15,7 @@ module \$_DFF_NP1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED( module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule +`ifndef NO_LUT module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; @@ -82,3 +83,4 @@ module \$lut (A, Y); end endgenerate endmodule +`endif |