iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-1/+1
*	verilog: significant block scoping improvements	Zachary Snow	2021-01-31	1	-2/+4
*	Remove EXPLICIT_CARRY logic.	Keith Rothman	2020-07-23	1	-113/+1
*	Add force_downto and force_upto wire attributes.	Marcelina Kościelnicka	2020-05-19	1	-0/+23
*	xilinx: Initial support for LUT4 devices.	Marcin Kościelnicki	2020-02-07	1	-11/+42
*	Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk	Eddie Hung	2020-02-06	1	-4/+5
*	Fix/cleanup +/xilinx/arith_map.v	Eddie Hung	2020-02-06	1	-111/+44
*	Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623	Eddie Hung	2020-01-17	1	-117/+82
*	+/xilinx/arith_map.v fix $lcu rule	Eddie Hung	2020-01-17	1	-6/+6
*	Instead of MUXCY/XORCY use CARRY4 (with timing)	Eddie Hung	2019-05-21	1	-2/+2
*	Changes required for VPR place and route synth_xilinx.	Keith Rothman	2019-03-01	1	-7/+275
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-2/+2
*	Various cleanups in xilinx techlib	Clifford Wolf	2015-01-18	1	-0/+91