iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Rename abc_* names/attributes to more precisely be abc9_*	Eddie Hung	2019-10-04	1	-211/+0
*	Add (* techmap_autopurge *) to abc_unmap.v too	Eddie Hung	2019-09-23	1	-11/+11
*	Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"	Eddie Hung	2019-09-23	1	-38/+38
*	Remove (* techmap_autopurge *) from abc_unmap.v since no effect	Eddie Hung	2019-09-23	1	-38/+38
*	$__ABC_REG to have WIDTH parameter	Eddie Hung	2019-09-19	1	-1/+2
*	Fix DSP48E1 timing by breaking P path if MREG or PREG	Eddie Hung	2019-09-19	1	-2/+4
*	Revert "Different approach to timing"	Eddie Hung	2019-09-19	1	-2/+2
*	Different approach to timing	Eddie Hung	2019-09-19	1	-2/+2
*	Use (* techmap_autopurge *) to suppress techmap warnings	Eddie Hung	2019-09-19	1	-39/+44
*	Add no MULT no DPORT config	Eddie Hung	2019-09-13	1	-2/+2
*	Add support for MULT and DPORT	Eddie Hung	2019-09-13	1	-5/+4
*	Initial DSP48E1 box support	Eddie Hung	2019-09-12	1	-0/+176
*	xilinx to use abc_map.v with -max_iter 1	Eddie Hung	2019-08-20	1	-94/+2
*	Remove sequential extension	Eddie Hung	2019-08-20	1	-119/+0
*	Wrap SRL{16,32} too	Eddie Hung	2019-08-20	1	-1/+36
*	Wrap LUTRAMs in order to capture comb/seq behaviour	Eddie Hung	2019-08-20	1	-0/+64
*	Use abc_{map,unmap,model}.v	Eddie Hung	2019-08-20	1	-0/+140