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* intel_alm: M10K write-enable is negative-trueLofty2022-03-096-7/+28
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* intel_alm: disable 256x40 M10K modeLofty2021-12-221-9/+3
| | | | | This BRAM mode uses both address ports, making it effectively single-port. Since memory_bram can't presently map to single-port memories, remove it.
* intel_alm: preliminary Arria V supportLofty2021-11-256-7/+199
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* CycloneV: Add (passthrough) support for cyclonev_oscillatorOlivier Galibert2021-10-171-1/+11
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* CycloneV: Add (passthrough) support for ↵Olivier Galibert2021-10-171-0/+8
| | | | cyclonev_hps_interface_mpu_general_purpose
* Fix files with CRLF line endingsClaire Xenia Wolf2021-06-091-31/+31
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* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-082-2/+2
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* intel_alm: Fix illegal carry chainsgatecat2021-05-152-3/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* intel_alm: Add global buffer insertiongatecat2021-05-156-4/+78
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* intel_alm: Add IO buffer insertiongatecat2021-05-156-7/+127
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Blackbox all whiteboxes after synthesisgatecat2021-03-171-0/+1
| | | | | | | This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me>
* intel_alm: better map wide but shallow multipliesDan Ravensloft2020-08-281-2/+6
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* intel_alm: Add multiply signedness to cellsDan Ravensloft2020-08-265-10/+103
| | | | | | Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells.
* intel: move Cyclone V support to intel_almDan Ravensloft2020-08-203-1/+153
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* intel_alm: fix typo in MISTRAL_MUL27X27 cell nameDan Ravensloft2020-08-131-1/+1
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* intel_alm: add more megafunctions. NFC.Dan Ravensloft2020-08-121-0/+431
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* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-3/+2
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* intel_alm: direct M10K instantiationDan Ravensloft2020-07-277-39/+127
| | | | This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
* intel_alm: increase abc9 -WDan Ravensloft2020-07-261-1/+1
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* intel_alm: add additional ABC9 timingsDan Ravensloft2020-07-234-72/+91
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* Revert "intel_alm: direct M10K instantiation"Lofty2020-07-137-122/+38
| | | | This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
* intel_alm: direct M10K instantiationDan Ravensloft2020-07-057-38/+122
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* intel_alm: DSP inferenceDan Ravensloft2020-07-056-9/+186
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* synth_intel_alm: Use dfflegalize.Marcelina Kościelnicka2020-07-042-121/+9
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* Improve MISTRAL_FF specify rulesDan Ravensloft2020-07-041-5/+4
| | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FFEddie Hung2020-07-042-47/+2
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* intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLYEddie Hung2020-07-044-4/+4
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* intel_alm: ABC9 sequential optimisationsDan Ravensloft2020-07-047-19/+149
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* Use C++11 final/override keywords.whitequark2020-06-181-4/+4
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* intel_alm: fix DFFE matchingDan Ravensloft2020-06-111-1/+1
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* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-192-0/+8
| | | | Fixes #2058.
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-141-1/+0
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* intel_alm: direct LUTRAM cell instantiationDan Ravensloft2020-05-078-52/+143
| | | | | | | | | | By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
* intel_alm: cleanup duplicationDan Ravensloft2020-04-245-113/+64
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* intel_alm: work around a Quartus ICEDan Ravensloft2020-04-231-0/+10
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* intel_alm: Documentation improvementsDan Ravensloft2020-04-213-14/+127
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* synth_intel_alm: VQM supportDan Ravensloft2020-04-152-6/+3
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* synth_intel_alm: alternative synthesis for Intel FPGAsDan Ravensloft2020-04-1517-0/+1453
By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
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