| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add force_downto and force_upto wire attributes. | Marcelina Kościelnicka | 2020-05-19 | 2 | -0/+8 |
| * | synth_*: no need to explicitly read +/abc9_model.v | Eddie Hung | 2020-05-14 | 1 | -1/+0 |
| * | intel_alm: direct LUTRAM cell instantiation | Dan Ravensloft | 2020-05-07 | 8 | -52/+143 |
| * | intel_alm: cleanup duplication | Dan Ravensloft | 2020-04-24 | 5 | -113/+64 |
| * | intel_alm: work around a Quartus ICE | Dan Ravensloft | 2020-04-23 | 1 | -0/+10 |
| * | intel_alm: Documentation improvements | Dan Ravensloft | 2020-04-21 | 3 | -14/+127 |
| * | synth_intel_alm: VQM support | Dan Ravensloft | 2020-04-15 | 2 | -6/+3 |
| * | synth_intel_alm: alternative synthesis for Intel FPGAs | Dan Ravensloft | 2020-04-15 | 17 | -0/+1453 |
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index : iCE40/yosys | |
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