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path: root/techlibs/intel/synth_intel.cc
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* Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-1/+1
* synth_intel: a10gx -> arria10gxDan Ravensloft2019-12-101-3/+3
* synth_intel: cyclone10 -> cyclone10lpDan Ravensloft2019-12-101-3/+3
* Merge branch 'ZirconiumX-synth_intel_m9k'Clifford Wolf2019-07-251-3/+9
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| * intel: Map M9K BRAM only on families that have itDan Ravensloft2019-07-231-3/+10
* | intel: Make -noiopads the defaultDan Ravensloft2019-07-241-8/+8
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* Merge pull request #1208 from ZirconiumX/intel_cleanupsDavid Shah2019-07-181-29/+14
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| * synth_intel: Use stringfDan Ravensloft2019-07-181-7/+2
| * synth_intel: s/not family/no family/Dan Ravensloft2019-07-181-2/+2
| * intel_synth: Fix help messageBen Widawsky2019-07-181-1/+1
| * intel_synth: Small code cleanup to remove if ladderBen Widawsky2019-07-181-28/+10
| * intel_synth: Make family explicit and matchBen Widawsky2019-07-181-2/+6
| * intel_synth: Minor code cleanupsBen Widawsky2019-07-181-2/+6
* | synth_intel: rename for consistency with #1184Dan Ravensloft2019-07-181-4/+4
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* synth_intel: Warn about untested Quartus backendDan Ravensloft2019-07-071-0/+3
* Fix formatting for synth_intel.ccBen Widawsky2019-05-091-222/+211
* Unify usage of noflatten among architecturesMiodrag Milanovic2019-01-041-2/+2
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-6/+6
* Add "synth_intel --noiopads"Clifford Wolf2018-04-301-2/+11
* Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal val...c60k282018-03-311-4/+23
* Add "dffinit -highlow" and fix synth_intelClifford Wolf2018-01-091-1/+1
* Initial Cyclone 10 supportdh732017-11-081-1/+5
* Clean whitespace and permissions in techlibs/intelLarry Doolittle2017-10-051-3/+3
* Rename "write_verilog -nobasenradix" to "write_verilog -decimal"Clifford Wolf2017-10-031-4/+1
* Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ...dh732017-10-011-0/+241