Add force_downto and force_upto wire attributes.

Fixes #2058.

2 files changed, 9 insertions, 0 deletions

diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v
index ed4140e44..3950e882b 100644
--- a/techlibs/ice40/arith_map.v
+++ b/techlibs/ice40/arith_map.v
@@ -25,21 +25,29 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
 	parameter B_WIDTH = 1;
 	parameter Y_WIDTH = 1;
 
+	(* force_downto *)
 	input [A_WIDTH-1:0] A;
+	(* force_downto *)
 	input [B_WIDTH-1:0] B;
+	(* force_downto *)
 	output [Y_WIDTH-1:0] X, Y;
 
 	input CI, BI;
+	(* force_downto *)
 	output [Y_WIDTH-1:0] CO;
 
 	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
 
+	(* force_downto *)
 	wire [Y_WIDTH-1:0] A_buf, B_buf;
 	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
 	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 
+	(* force_downto *)
 	wire [Y_WIDTH-1:0] AA = A_buf;
+	(* force_downto *)
 	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+	(* force_downto *)
 	wire [Y_WIDTH-1:0] C = {CO, CI};
 
 	genvar i;
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v
index e9ccca239..7e5c07879 100644
--- a/techlibs/ice40/cells_map.v
+++ b/techlibs/ice40/cells_map.v
@@ -2,6 +2,7 @@ module \$lut (A, Y);
   parameter WIDTH = 0;
   parameter LUT = 0;
 
+  (* force_downto *)
   input [WIDTH-1:0] A;
   output Y;