aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/ice40
Commit message (Collapse)AuthorAgeFilesLines
* ice40: Use dfflegalize.Marcelina Kościelnicka2020-07-054-208/+24
|
* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-232-9/+9
|
* Use C++11 final/override keywords.whitequark2020-06-185-13/+13
|
* Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTHXark2020-06-141-7/+7
|
* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-192-0/+9
| | | | Fixes #2058.
* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-141-1/+1
|
* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-141-0/+153
|
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-1/+1
| | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-141-1/+1
|
* ice40: synth_ice40 cleanupEddie Hung2020-05-141-13/+3
|
* ice40: add synth_ice40 -dff option, support with -abc9Eddie Hung2020-05-142-8/+41
|
* ice40: split out cells_map.v into ff_map.vEddie Hung2020-05-143-31/+29
|
* ice40: fix ICESTORM_LC process sensitivityEddie Hung2020-05-121-1/+1
|
* ice40: fix whitespaceEddie Hung2020-05-121-15/+14
|
* synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpadEddie Hung2020-05-041-8/+16
|
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-1/+0
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-102-1/+63
|\ | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
| * ice40: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-1/+3
| |
| * ice40: match memory inference attribute values case insensitive.whitequark2020-02-061-0/+1
| | | | | | | | LSE/Synplify use case insensitive matching.
| * ice40: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-061-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify appear to interpret attribute values insensitive to case. There is currently no way to do this in Yosys (attrmap can only change case of attribute names). * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
* | kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-024-75/+75
| |
* | kernel: use more ID::*Eddie Hung2020-04-023-17/+17
| |
* | Fix indentation in `techlibs/ice40/synth_ice40.cc`.Alberto Gonzalez2020-04-011-4/+4
| |
* | Merge pull request #1794 from YosysHQ/dave/mince-abc9-fixDavid Shah2020-03-211-0/+1
|\ \ | | | | | | ice40: Map unmapped 'mince' DFFs to gate level
| * | ice40: Map unmapped 'mince' DFFs to gate levelDavid Shah2020-03-201-0/+1
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ice40: Fix typos in SPRAM ABC9 timing specsSylvain Munaut2020-03-201-2/+2
|/ / | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | ice40: Fix SPRAM model to keep data stable if chipselect is lowSylvain Munaut2020-03-141-5/+8
| | | | | | | | | | | | | | | | According to the official simulation model, and also cross-checked on real hardware, the data output of the SPRAM when chipselect is low is kept stable. It doesn't go undefined. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | ice40: fix specify for ICE40_{LP,U}Eddie Hung2020-03-051-4/+4
| |
* | ice40: fix implicit signal in specify, also clamp negative times to 0Eddie Hung2020-03-041-22/+22
| |
* | Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabcN. Engelhardt2020-03-031-4/+22
|\ \ | | | | | | Add -flowmap option to `synth{,_ice40}`
| * | Add -flowmap to synth and synth_ice40Dan Ravensloft2020-02-281-4/+22
| |/
* | ice40: add delays to SB_CARRYEddie Hung2020-02-271-0/+30
| |
* | More +/ice40/cells_sim.v fixesEddie Hung2020-02-271-27/+27
| |
* | ice40: fix specify for inverted clocksEddie Hung2020-02-271-27/+27
| |
* | ice40: specify fixesEddie Hung2020-02-273-66/+66
| |
* | ice40: move over to specify blocks for -abc9Eddie Hung2020-02-2710-164/+1344
|/
* synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-051-0/+1
|
* Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwardsEddie Hung2020-01-271-1/+1
| | | | Just like Verilog...
* Import tests from #1628Eddie Hung2020-01-271-2/+2
|
* xilinx/ice40/ecp5: undo permuting LUT masks in lut_mapEddie Hung2020-01-271-7/+6
| | | | Now done in read_aiger
* Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warningsEddie Hung2020-01-274-6/+10
|\ | | | | ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
| * ice40: reduce ABC9 internal fanout warnings with a param for CI->I3Eddie Hung2020-01-244-6/+10
| |
* | ice40: add SB_SPRAM256KA arrival timeEddie Hung2020-01-241-0/+1
|/
* Merge pull request #1602 from niklasnisbeth/ice40-init-vals-warningDavid Shah2020-01-181-2/+8
|\ | | | | ice40: Demote conflicting FF init values to a warning
| * ice40: Demote conflicting FF init values to a warningNiklas Nisbeth2019-12-311-2/+8
| |
* | synth_ice40: call wreduce before mul2dspEddie Hung2020-01-171-1/+2
| |
* | synth_ice40: -abc2 to always use `abc` even if `-abc9`Eddie Hung2020-01-121-10/+10
| |
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-061-0/+2
|\ \
| * | Valid to have attribute starting with SB_CARRY.Miodrag Milanovic2020-01-041-0/+2
| | |
* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-021-2/+2
|\| |
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 06:25:44 +0000