| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth_*: call 'opt -fast' after 'techmap' | Eddie Hung | 2020-02-05 | 1 | -0/+1 |
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| * | Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards | Eddie Hung | 2020-01-27 | 1 | -1/+1 |
| | | | | | Just like Verilog... | ||||
| * | Import tests from #1628 | Eddie Hung | 2020-01-27 | 1 | -2/+2 |
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| * | xilinx/ice40/ecp5: undo permuting LUT masks in lut_map | Eddie Hung | 2020-01-27 | 1 | -7/+6 |
| | | | | | Now done in read_aiger | ||||
| * | Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings | Eddie Hung | 2020-01-27 | 4 | -6/+10 |
| |\ | | | | | ice40: reduce ABC9 internal fanout warnings with a param for CI->I3 | ||||
| | * | ice40: reduce ABC9 internal fanout warnings with a param for CI->I3 | Eddie Hung | 2020-01-24 | 4 | -6/+10 |
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| * | | ice40: add SB_SPRAM256KA arrival time | Eddie Hung | 2020-01-24 | 1 | -0/+1 |
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| * | Merge pull request #1602 from niklasnisbeth/ice40-init-vals-warning | David Shah | 2020-01-18 | 1 | -2/+8 |
| |\ | | | | | ice40: Demote conflicting FF init values to a warning | ||||
| | * | ice40: Demote conflicting FF init values to a warning | Niklas Nisbeth | 2019-12-31 | 1 | -2/+8 |
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| * | | synth_ice40: call wreduce before mul2dsp | Eddie Hung | 2020-01-17 | 1 | -1/+2 |
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| * | | synth_ice40: -abc2 to always use `abc` even if `-abc9` | Eddie Hung | 2020-01-12 | 1 | -10/+10 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2020-01-06 | 1 | -0/+2 |
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| | * | | Valid to have attribute starting with SB_CARRY. | Miodrag Milanovic | 2020-01-04 | 1 | -0/+2 |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2020-01-02 | 1 | -2/+2 |
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| | * | | Update doc that "-retime" calls abc with "-dff -D 1" | Eddie Hung | 2019-12-30 | 1 | -1/+1 |
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| | * | | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well"" | Eddie Hung | 2019-12-30 | 1 | -1/+1 |
| | |/ | | | | | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745. | ||||
| | * | Revert "Optimise write_xaiger" | Eddie Hung | 2019-12-20 | 1 | -5/+0 |
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| | * | Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup | Eddie Hung | 2019-12-19 | 1 | -0/+5 |
| | |\ | | | | | | | Optimise write_xaiger | ||||
| | | * | techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger | Eddie Hung | 2019-12-06 | 1 | -0/+5 |
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| * | | | Cleanup ice40 boxes | Eddie Hung | 2019-12-31 | 3 | -30/+43 |
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| * | | ice40_opt to restore attributes/name when unwrapping | Eddie Hung | 2019-12-09 | 1 | -0/+15 |
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| * | | Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4 | Eddie Hung | 2019-12-09 | 1 | -1/+1 |
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| * | | ice40_wrapcarry to really preserve attributes via -unwrap option | Eddie Hung | 2019-12-09 | 2 | -19/+1 |
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| * | | $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve | Eddie Hung | 2019-12-03 | 1 | -1/+1 |
| | | | | | | | | | name and attr | ||||
| * | | ice40_opt to ignore (* keep *) -ed cells | Eddie Hung | 2019-12-03 | 1 | -0/+5 |
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| * | Merge pull request #1490 from YosysHQ/clifford/autoname | Clifford Wolf | 2019-11-14 | 1 | -0/+1 |
| |\ | | | | | Add "autoname" pass and use it in "synth_ice40" | ||||
| | * | Add "autoname" pass and use it in "synth_ice40" | Clifford Wolf | 2019-11-13 | 1 | -0/+1 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim | Clifford Wolf | 2019-11-14 | 1 | -14/+436 |
| |\ \ | |/ |/| | ice40: Support for post-place-and-route timing simulations | ||||
| | * | ice40: Add post-pnr ICESTORM_RAM model and fix FFs | David Shah | 2019-10-23 | 1 | -2/+340 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | ice40: Support for post-pnr timing simulation | David Shah | 2019-10-23 | 1 | -12/+96 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg | Clifford Wolf | 2019-10-22 | 1 | -0/+1 |
| |\ \ | |/ |/| | Call memory_dff before DSP mapping to reserve registers (fixes #1447) | ||||
| | * | Call memory_dff before DSP mapping to reserve registers (fixes #1447) | N. Engelhardt | 2019-10-17 | 1 | -0/+1 |
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| * | | Makefile: don't assume python is called `python3` | Sean Cross | 2019-10-19 | 1 | -1/+1 |
| |/ | | | | | | | | | | | | | | | | On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross <sean@xobs.io> | ||||
| * | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 10 | -91/+90 |
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| * | Panic over. Model was elsewhere. Re-arrange for consistency | Eddie Hung | 2019-10-04 | 4 | -31/+3 |
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| * | Oops | Eddie Hung | 2019-10-04 | 1 | -1/+1 |
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| * | Ohmilord this wasn't added all this time!?! | Eddie Hung | 2019-10-04 | 1 | -0/+29 |
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| * | Re-order | Eddie Hung | 2019-09-27 | 1 | -1/+1 |
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| * | select once | Eddie Hung | 2019-09-26 | 1 | -5/+7 |
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| * | Stop trying to be too smart by prematurely optimising | Eddie Hung | 2019-09-26 | 1 | -3/+5 |
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| * | Only wreduce on t:$add | Eddie Hung | 2019-09-25 | 1 | -1/+1 |
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| * | Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40 | Eddie Hung | 2019-09-20 | 1 | -2/+1 |
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| * | Revert "Move mul2dsp before wreduce" | Eddie Hung | 2019-09-20 | 1 | -4/+5 |
| | | | | | This reverts commit e4f4f6a9d5cf8bb23870fc483f16f66c80ceebab. | ||||
| * | Move mul2dsp before wreduce | Eddie Hung | 2019-09-20 | 1 | -5/+4 |
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| * | Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2 | Eddie Hung | 2019-09-19 | 1 | -1/+3 |
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| * | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-05 | 2 | -22/+175 |
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| | * | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-30 | 3 | -3/+3 |
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| | * | | Comment out SB_MAC16 arrival time for now, need to handle all its modes | Eddie Hung | 2019-08-28 | 1 | -1/+1 |
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| | * | | Add arrival for SB_MAC16.O | Eddie Hung | 2019-08-28 | 1 | -0/+1 |
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| | * | | Add arrival times for U | Eddie Hung | 2019-08-28 | 1 | -0/+26 |
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index : iCE40/yosys | |
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