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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-12-20 12:05:45 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-20 12:05:45 -0800 |
| commit | 10e82e103f7b95d5a50d2ac85bc8e07e4461e388 (patch) | |
| tree | 3332182623313ac4aedc9c28adf4deb3a6fc70d6 /techlibs/ice40 | |
| parent | 319cba70d37eafdb8bbd3ddf6a0f9c238d53d0c2 (diff) | |
| download | yosys-10e82e103f7b95d5a50d2ac85bc8e07e4461e388.tar.gz yosys-10e82e103f7b95d5a50d2ac85bc8e07e4461e388.tar.bz2 yosys-10e82e103f7b95d5a50d2ac85bc8e07e4461e388.zip | |
Revert "Optimise write_xaiger"
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 5073ba917..ed7a16c08 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -350,11 +350,6 @@ struct SynthIce40Pass : public ScriptPass } if (!noabc) { if (abc == "abc9") { - run("select -set abc9_boxes A:abc9_box_id A:whitebox=1"); - run("wbflip @abc9_boxes"); - run("techmap -autoproc @abc9_boxes"); - run("aigmap @abc9_boxes"); - run("wbflip @abc9_boxes"); run("read_verilog -icells -lib +/ice40/abc9_model.v"); int wire_delay; if (device_opt == "lp") |