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* Merge pull request #1794 from YosysHQ/dave/mince-abc9-fixDavid Shah2020-03-211-0/+1
|\ | | | | ice40: Map unmapped 'mince' DFFs to gate level
| * ice40: Map unmapped 'mince' DFFs to gate levelDavid Shah2020-03-201-0/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ice40: Fix typos in SPRAM ABC9 timing specsSylvain Munaut2020-03-201-2/+2
|/ | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Fix SPRAM model to keep data stable if chipselect is lowSylvain Munaut2020-03-141-5/+8
| | | | | | | | According to the official simulation model, and also cross-checked on real hardware, the data output of the SPRAM when chipselect is low is kept stable. It doesn't go undefined. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: fix specify for ICE40_{LP,U}Eddie Hung2020-03-051-4/+4
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* ice40: fix implicit signal in specify, also clamp negative times to 0Eddie Hung2020-03-041-22/+22
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* Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabcN. Engelhardt2020-03-031-4/+22
|\ | | | | Add -flowmap option to `synth{,_ice40}`
| * Add -flowmap to synth and synth_ice40Dan Ravensloft2020-02-281-4/+22
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* | ice40: add delays to SB_CARRYEddie Hung2020-02-271-0/+30
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* | More +/ice40/cells_sim.v fixesEddie Hung2020-02-271-27/+27
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* | ice40: fix specify for inverted clocksEddie Hung2020-02-271-27/+27
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* | ice40: specify fixesEddie Hung2020-02-273-66/+66
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* | ice40: move over to specify blocks for -abc9Eddie Hung2020-02-2710-164/+1344
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* synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-051-0/+1
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* Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwardsEddie Hung2020-01-271-1/+1
| | | | Just like Verilog...
* Import tests from #1628Eddie Hung2020-01-271-2/+2
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* xilinx/ice40/ecp5: undo permuting LUT masks in lut_mapEddie Hung2020-01-271-7/+6
| | | | Now done in read_aiger
* Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warningsEddie Hung2020-01-274-6/+10
|\ | | | | ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
| * ice40: reduce ABC9 internal fanout warnings with a param for CI->I3Eddie Hung2020-01-244-6/+10
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* | ice40: add SB_SPRAM256KA arrival timeEddie Hung2020-01-241-0/+1
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* Merge pull request #1602 from niklasnisbeth/ice40-init-vals-warningDavid Shah2020-01-181-2/+8
|\ | | | | ice40: Demote conflicting FF init values to a warning
| * ice40: Demote conflicting FF init values to a warningNiklas Nisbeth2019-12-311-2/+8
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* | synth_ice40: call wreduce before mul2dspEddie Hung2020-01-171-1/+2
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* | synth_ice40: -abc2 to always use `abc` even if `-abc9`Eddie Hung2020-01-121-10/+10
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-061-0/+2
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| * | Valid to have attribute starting with SB_CARRY.Miodrag Milanovic2020-01-041-0/+2
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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-021-2/+2
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| * | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-1/+1
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| * | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-1/+1
| |/ | | | | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
| * Revert "Optimise write_xaiger"Eddie Hung2019-12-201-5/+0
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| * Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-191-0/+5
| |\ | | | | | | Optimise write_xaiger
| | * techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-061-0/+5
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* | | Cleanup ice40 boxesEddie Hung2019-12-313-30/+43
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* | ice40_opt to restore attributes/name when unwrappingEddie Hung2019-12-091-0/+15
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* | Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4Eddie Hung2019-12-091-1/+1
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* | ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-092-19/+1
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* | $__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserveEddie Hung2019-12-031-1/+1
| | | | | | | | name and attr
* | ice40_opt to ignore (* keep *) -ed cellsEddie Hung2019-12-031-0/+5
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* Merge pull request #1490 from YosysHQ/clifford/autonameClifford Wolf2019-11-141-0/+1
|\ | | | | Add "autoname" pass and use it in "synth_ice40"
| * Add "autoname" pass and use it in "synth_ice40"Clifford Wolf2019-11-131-0/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #1465 from YosysHQ/dave/ice40_timing_simClifford Wolf2019-11-141-14/+436
|\ \ | |/ |/| ice40: Support for post-place-and-route timing simulations
| * ice40: Add post-pnr ICESTORM_RAM model and fix FFsDavid Shah2019-10-231-2/+340
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ice40: Support for post-pnr timing simulationDavid Shah2019-10-231-12/+96
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #1452 from nakengelhardt/fix_dsp_mem_regClifford Wolf2019-10-221-0/+1
|\ \ | |/ |/| Call memory_dff before DSP mapping to reserve registers (fixes #1447)
| * Call memory_dff before DSP mapping to reserve registers (fixes #1447)N. Engelhardt2019-10-171-0/+1
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* | Makefile: don't assume python is called `python3`Sean Cross2019-10-191-1/+1
|/ | | | | | | | | | | | | | | | On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross <sean@xobs.io>
* Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-0410-91/+90
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* Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-044-31/+3
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* OopsEddie Hung2019-10-041-1/+1
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* Ohmilord this wasn't added all this time!?!Eddie Hung2019-10-041-0/+29
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