iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	verilog: significant block scoping improvements	Zachary Snow	2021-01-31	1	-33/+40
*	Replace opt_rmdff with opt_dff.	Marcelina Kościelnicka	2020-08-07	1	-3/+1
*	synth_ice40: Use opt_dff.	Marcelina Kościelnicka	2020-07-30	4	-142/+6
*	ice40: Use dfflegalize.	Marcelina Kościelnicka	2020-07-05	4	-208/+24
*	Update dff2dffe, dff2dffs, zinit to new FF types.	Marcelina Kościelnicka	2020-06-23	2	-9/+9
*	Use C++11 final/override keywords.	whitequark	2020-06-18	5	-13/+13
*	Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH	Xark	2020-06-14	1	-7/+7
*	Add force_downto and force_upto wire attributes.	Marcelina Kościelnicka	2020-05-19	2	-0/+9
*	xilinx/ice40/ecp5: zinit requires selected wires, so select them all	Eddie Hung	2020-05-14	1	-1/+1
*	xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells	Eddie Hung	2020-05-14	1	-0/+153
*	abc9_ops: add -prep_bypass for auto bypass boxes; refactor	Eddie Hung	2020-05-14	1	-1/+1
*	synth_*: no need to explicitly read +/abc9_model.v	Eddie Hung	2020-05-14	1	-1/+1
*	ice40: synth_ice40 cleanup	Eddie Hung	2020-05-14	1	-13/+3
*	ice40: add synth_ice40 -dff option, support with -abc9	Eddie Hung	2020-05-14	2	-8/+41
*	ice40: split out cells_map.v into ff_map.v	Eddie Hung	2020-05-14	3	-31/+29
*	ice40: fix ICESTORM_LC process sensitivity	Eddie Hung	2020-05-12	1	-1/+1
*	ice40: fix whitespace	Eddie Hung	2020-05-12	1	-15/+14
*	synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad	Eddie Hung	2020-05-04	1	-8/+16
*	Get rid of dffsr2dff.	Marcelina Kościelnicka	2020-04-15	1	-1/+0
*	Merge pull request #1603 from whitequark/ice40-ram_style	whitequark	2020-04-10	2	-1/+63
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\| *	ice40: do not map FFRAM if explicitly requested otherwise.	whitequark	2020-04-03	1	-1/+3
\| *	ice40: match memory inference attribute values case insensitive.	whitequark	2020-02-06	1	-0/+1
\| *	ice40: add support for both 1364.1 and LSE RAM/ROM attributes.	whitequark	2020-02-06	1	-0/+59
* \|	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	4	-75/+75
* \|	kernel: use more ID::*	Eddie Hung	2020-04-02	3	-17/+17
* \|	Fix indentation in `techlibs/ice40/synth_ice40.cc`.	Alberto Gonzalez	2020-04-01	1	-4/+4
* \|	Merge pull request #1794 from YosysHQ/dave/mince-abc9-fix	David Shah	2020-03-21	1	-0/+1
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\| * \|	ice40: Map unmapped 'mince' DFFs to gate level	David Shah	2020-03-20	1	-0/+1
* \| \|	ice40: Fix typos in SPRAM ABC9 timing specs	Sylvain Munaut	2020-03-20	1	-2/+2
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* \|	ice40: Fix SPRAM model to keep data stable if chipselect is low	Sylvain Munaut	2020-03-14	1	-5/+8
* \|	ice40: fix specify for ICE40_{LP,U}	Eddie Hung	2020-03-05	1	-4/+4
* \|	ice40: fix implicit signal in specify, also clamp negative times to 0	Eddie Hung	2020-03-04	1	-22/+22
* \|	Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabc	N. Engelhardt	2020-03-03	1	-4/+22
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\| * \|	Add -flowmap to synth and synth_ice40	Dan Ravensloft	2020-02-28	1	-4/+22
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* \|	ice40: add delays to SB_CARRY	Eddie Hung	2020-02-27	1	-0/+30
* \|	More +/ice40/cells_sim.v fixes	Eddie Hung	2020-02-27	1	-27/+27
* \|	ice40: fix specify for inverted clocks	Eddie Hung	2020-02-27	1	-27/+27
* \|	ice40: specify fixes	Eddie Hung	2020-02-27	3	-66/+66
* \|	ice40: move over to specify blocks for -abc9	Eddie Hung	2020-02-27	10	-164/+1344
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*	synth_*: call 'opt -fast' after 'techmap'	Eddie Hung	2020-02-05	1	-0/+1
*	Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards	Eddie Hung	2020-01-27	1	-1/+1
*	Import tests from #1628	Eddie Hung	2020-01-27	1	-2/+2
*	xilinx/ice40/ecp5: undo permuting LUT masks in lut_map	Eddie Hung	2020-01-27	1	-7/+6
*	Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings	Eddie Hung	2020-01-27	4	-6/+10
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\| *	ice40: reduce ABC9 internal fanout warnings with a param for CI->I3	Eddie Hung	2020-01-24	4	-6/+10
* \|	ice40: add SB_SPRAM256KA arrival time	Eddie Hung	2020-01-24	1	-0/+1
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*	Merge pull request #1602 from niklasnisbeth/ice40-init-vals-warning	David Shah	2020-01-18	1	-2/+8
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\| *	ice40: Demote conflicting FF init values to a warning	Niklas Nisbeth	2019-12-31	1	-2/+8
* \|	synth_ice40: call wreduce before mul2dsp	Eddie Hung	2020-01-17	1	-1/+2
* \|	synth_ice40: -abc2 to always use `abc` even if `-abc9`	Eddie Hung	2020-01-12	1	-10/+10