aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/ice40/synth_ice40.cc
Commit message (Expand)AuthorAgeFilesLines
* Fitting help messages to 80 character widthKrystalDelusion2022-08-241-2/+2
* Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.Marcelina Kościelnicka2022-06-021-3/+19
* ice40: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-7/+20
* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-291-1/+1
* ice40: Fix LUT input indices in opt_lut -dlogic (again).Marcelina Kościelnicka2021-07-101-1/+1
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
* Blackbox all whiteboxes after synthesisgatecat2021-03-171-0/+1
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-3/+1
* synth_ice40: Use opt_dff.Marcelina Kościelnicka2020-07-301-8/+4
* ice40: Use dfflegalize.Marcelina Kościelnicka2020-07-051-5/+4
* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-231-1/+1
* Use C++11 final/override keywords.whitequark2020-06-181-5/+5
* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-141-1/+1
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-1/+1
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-141-1/+1
* ice40: synth_ice40 cleanupEddie Hung2020-05-141-13/+3
* ice40: add synth_ice40 -dff option, support with -abc9Eddie Hung2020-05-141-8/+28
* ice40: fix whitespaceEddie Hung2020-05-121-15/+14
* synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpadEddie Hung2020-05-041-8/+16
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-1/+0
* Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-101-1/+3
|\
| * ice40: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-1/+3
* | Fix indentation in `techlibs/ice40/synth_ice40.cc`.Alberto Gonzalez2020-04-011-4/+4
* | ice40: Map unmapped 'mince' DFFs to gate levelDavid Shah2020-03-201-0/+1
* | Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabcN. Engelhardt2020-03-031-4/+22
|\ \
| * | Add -flowmap to synth and synth_ice40Dan Ravensloft2020-02-281-4/+22
| |/
* | ice40: specify fixesEddie Hung2020-02-271-9/+9
* | ice40: move over to specify blocks for -abc9Eddie Hung2020-02-271-3/+3
|/
* synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-051-0/+1
* synth_ice40: call wreduce before mul2dspEddie Hung2020-01-171-1/+2
* synth_ice40: -abc2 to always use `abc` even if `-abc9`Eddie Hung2020-01-121-10/+10
* Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-1/+1
* Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-1/+1
* Revert "Optimise write_xaiger"Eddie Hung2019-12-201-5/+0
* Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-191-0/+5
|\
| * techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-061-0/+5
* | ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-091-0/+1
|/
* Add "autoname" pass and use it in "synth_ice40"Clifford Wolf2019-11-131-0/+1
* Call memory_dff before DSP mapping to reserve registers (fixes #1447)N. Engelhardt2019-10-171-0/+1
* Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-2/+2
* Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-041-1/+2
* Re-orderEddie Hung2019-09-271-1/+1
* select onceEddie Hung2019-09-261-5/+7
* Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-261-3/+5
* Only wreduce on t:$addEddie Hung2019-09-251-1/+1
* Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40Eddie Hung2019-09-201-2/+1
* Revert "Move mul2dsp before wreduce"Eddie Hung2019-09-201-4/+5
* Move mul2dsp before wreduceEddie Hung2019-09-201-5/+4
* Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2Eddie Hung2019-09-191-1/+3
* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-051-1/+8
|\