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| author | whitequark <whitequark@whitequark.org> | 2020-04-10 14:51:01 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-10 14:51:01 +0000 |
| commit | 93ef516d919b40ace2099bc7586bfda8648f0757 (patch) | |
| tree | ab7e043e1c9d5cd1e6ff5258fd1e6709081200a0 /techlibs/ice40/synth_ice40.cc | |
| parent | 93c6c6779861d7b41fae1b87d54790e0a9555b80 (diff) | |
| parent | 763401fc827d444bfef5a10ff658a3bf7e89b76c (diff) | |
| download | yosys-93ef516d919b40ace2099bc7586bfda8648f0757.tar.gz yosys-93ef516d919b40ace2099bc7586bfda8648f0757.tar.bz2 yosys-93ef516d919b40ace2099bc7586bfda8648f0757.zip | |
Merge pull request #1603 from whitequark/ice40-ram_style
ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
Diffstat (limited to 'techlibs/ice40/synth_ice40.cc')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 59ada8bae..463e80ee2 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -319,7 +319,9 @@ struct SynthIce40Pass : public ScriptPass if (check_label("map_ffram")) { run("opt -fast -mux_undef -undriven -fine"); - run("memory_map"); + run("memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block " + "-attr syn_ramstyle=auto -attr syn_ramstyle=registers " + "-attr syn_romstyle=auto -attr syn_romstyle=logic"); run("opt -undriven -fine"); } |