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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 09:58:20 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | fb60d82971a9de5312467c4c192148ab546504dc (patch) | |
| tree | 0bdde7771d37941e1867a344c281ea01f8fc9ee3 /techlibs/ice40/synth_ice40.cc | |
| parent | a85c55113fbaf62ade66e583942782820fd0e9ff (diff) | |
| download | yosys-fb60d82971a9de5312467c4c192148ab546504dc.tar.gz yosys-fb60d82971a9de5312467c4c192148ab546504dc.tar.bz2 yosys-fb60d82971a9de5312467c4c192148ab546504dc.zip | |
ice40: move over to specify blocks for -abc9
Diffstat (limited to 'techlibs/ice40/synth_ice40.cc')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index fdb203dcb..7466ef1c2 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -245,7 +245,7 @@ struct SynthIce40Pass : public ScriptPass define = "-D ICE40_U"; else define = "-D ICE40_HX"; - run("read_verilog " + define + " -lib +/ice40/cells_sim.v"); + run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); run("proc"); } @@ -352,7 +352,7 @@ struct SynthIce40Pass : public ScriptPass } if (!noabc) { if (abc9) { - run("read_verilog -icells -lib +/ice40/abc9_model.v"); + run("read_verilog -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v"); int wire_delay; if (device_opt == "lp") wire_delay = 400; @@ -360,7 +360,7 @@ struct SynthIce40Pass : public ScriptPass wire_delay = 750; else wire_delay = 250; - run(stringf("abc9 -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str())); + run(stringf("abc9 -W %d", wire_delay, device_opt.c_str(), device_opt.c_str())); } else run("abc -dress -lut 4", "(skip if -noabc)"); |