iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Get rid of dffsr2dff.	Marcelina Kościelnicka	2020-04-15	1	-1/+0
*	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	2	-29/+29
*	synth_*: call 'opt -fast' after 'techmap'	Eddie Hung	2020-02-05	1	-0/+1
*	Merge pull request #1604 from whitequark/unify-ram-naming	whitequark	2020-01-02	3	-6/+18
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\| *	Harmonize BRAM/LUTRAM descriptions across all of Yosys.	whitequark	2020-01-01	3	-6/+18
* \|	Update doc that "-retime" calls abc with "-dff -D 1"	Eddie Hung	2019-12-30	1	-2/+2
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*	FF should be initialized to 0	Miodrag Milanovic	2019-10-04	1	-1/+3
*	Add missing latch mapping	Miodrag Milanovic	2019-10-04	1	-0/+12
*	better handling of lut and begin/end add	Miodrag Milanovic	2019-09-18	1	-4/+10
*	Added simulation models for Efinix and Anlogic	Miodrag Milanovic	2019-09-15	1	-2/+62
*	Fix missing newline at end of file	Clifford Wolf	2019-08-22	1	-1/+1
*	Fix formating	Miodrag Milanovic	2019-08-11	1	-2/+2
*	one bit enable signal	Miodrag Milanovic	2019-08-11	1	-1/+1
*	fix mixing signals on FF mapping	Miodrag Milanovic	2019-08-11	1	-4/+4
*	Replaced custom step with setundef	Miodrag Milanovic	2019-08-11	3	-91/+1
*	Fixed data width	Miodrag Milanovic	2019-08-11	1	-2/+2
*	Adding new pass to fix carry chain	Miodrag Milanovic	2019-08-11	3	-0/+124
*	cleanup	Miodrag Milanovic	2019-08-11	1	-4/+7
*	Fix CO	Miodrag Milanovic	2019-08-09	1	-26/+24
*	clock for ram trough gbuf	Miodrag Milanovic	2019-08-04	1	-0/+6
*	Added bram support	Miodrag Milanovic	2019-08-04	6	-1/+260
*	Custom step to add global clock buffers	Miodrag Milanovic	2019-08-03	4	-1/+129
*	Initial EFINIX support	Miodrag Milanovic	2019-08-03	5	-0/+370