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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-11 17:05:24 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-11 17:05:24 +0200 |
| commit | 2897fe4d09118e37934b7e76f4990cc1d69a0cb5 (patch) | |
| tree | 9c4a6b2fcc10c9edf3b5a482e57dda5d6883bd1c /techlibs/efinix | |
| parent | ead2b52b5a123e2c93578555de394a7a406e1fa5 (diff) | |
| download | yosys-2897fe4d09118e37934b7e76f4990cc1d69a0cb5.tar.gz yosys-2897fe4d09118e37934b7e76f4990cc1d69a0cb5.tar.bz2 yosys-2897fe4d09118e37934b7e76f4990cc1d69a0cb5.zip | |
Fix formating
Diffstat (limited to 'techlibs/efinix')
| -rw-r--r-- | techlibs/efinix/arith_map.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/efinix/arith_map.v b/techlibs/efinix/arith_map.v index 56e1b039f..178f57bc5 100644 --- a/techlibs/efinix/arith_map.v +++ b/techlibs/efinix/arith_map.v @@ -33,8 +33,8 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO); input CI, BI; output [Y_WIDTH-1:0] CO; - wire CIx; - wire [Y_WIDTH-1:0] COx; + wire CIx; + wire [Y_WIDTH-1:0] COx; wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; |