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author | whitequark <whitequark@whitequark.org> | 2020-01-02 21:06:17 +0000 |
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committer | GitHub <noreply@github.com> | 2020-01-02 21:06:17 +0000 |
commit | f8d5920a7e61f78873b7bf49dd7e8f3a83f7adf3 (patch) | |
tree | e7c5b19ffae2bfc40e682f696d2ae40513717ad7 /techlibs/efinix | |
parent | ef6548203cca239a98b00ea652a92fe3e20f97d7 (diff) | |
parent | 550310e2647c7aac1e49b79d9ff912436103062f (diff) | |
download | yosys-f8d5920a7e61f78873b7bf49dd7e8f3a83f7adf3.tar.gz yosys-f8d5920a7e61f78873b7bf49dd7e8f3a83f7adf3.tar.bz2 yosys-f8d5920a7e61f78873b7bf49dd7e8f3a83f7adf3.zip |
Merge pull request #1604 from whitequark/unify-ram-naming
Harmonize BRAM/LUTRAM descriptions across all of Yosys
Diffstat (limited to 'techlibs/efinix')
-rw-r--r-- | techlibs/efinix/Makefile.inc | 2 | ||||
-rw-r--r-- | techlibs/efinix/brams.txt (renamed from techlibs/efinix/bram.txt) | 0 | ||||
-rw-r--r-- | techlibs/efinix/synth_efinix.cc | 22 |
3 files changed, 18 insertions, 6 deletions
diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc index 5013f7fc1..69665982c 100644 --- a/techlibs/efinix/Makefile.inc +++ b/techlibs/efinix/Makefile.inc @@ -7,4 +7,4 @@ $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_sim.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/brams_map.v)) -$(eval $(call add_share_file,share/efinix,techlibs/efinix/bram.txt)) +$(eval $(call add_share_file,share/efinix,techlibs/efinix/brams.txt)) diff --git a/techlibs/efinix/bram.txt b/techlibs/efinix/brams.txt index 0b3fd9308..0b3fd9308 100644 --- a/techlibs/efinix/bram.txt +++ b/techlibs/efinix/brams.txt diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc index 6fe0182ac..0efd91708 100644 --- a/techlibs/efinix/synth_efinix.cc +++ b/techlibs/efinix/synth_efinix.cc @@ -60,6 +60,9 @@ struct SynthEfinixPass : public ScriptPass log(" -retime\n"); log(" run 'abc' with '-dff -D 1' options\n"); log("\n"); + log(" -nobram\n"); + log(" do not use EFX_RAM_5K cells in output netlist\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -67,7 +70,7 @@ struct SynthEfinixPass : public ScriptPass } string top_opt, edif_file, json_file; - bool flatten, retime; + bool flatten, retime, nobram; void clear_flags() YS_OVERRIDE { @@ -76,6 +79,7 @@ struct SynthEfinixPass : public ScriptPass json_file = ""; flatten = true; retime = false; + nobram = false; } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE @@ -114,6 +118,10 @@ struct SynthEfinixPass : public ScriptPass retime = true; continue; } + if (args[argidx] == "-nobram") { + nobram = true; + continue; + } break; } extra_args(args, argidx, design); @@ -150,18 +158,22 @@ struct SynthEfinixPass : public ScriptPass run("synth -run coarse"); } - if (check_label("map_bram", "(skip if -nobram)")) + if (!nobram || check_label("map_bram", "(skip if -nobram)")) { - run("memory_bram -rules +/efinix/bram.txt"); + run("memory_bram -rules +/efinix/brams.txt"); run("techmap -map +/efinix/brams_map.v"); run("setundef -zero -params t:EFX_RAM_5K"); } - if (check_label("fine")) + if (check_label("map_ffram")) { run("opt -fast -mux_undef -undriven -fine"); run("memory_map"); run("opt -undriven -fine"); + } + + if (check_label("map_gates")) + { run("techmap -map +/techmap.v -map +/efinix/arith_map.v"); if (retime || help_mode) run("abc -dff -D 1", "(only if -retime)"); @@ -194,7 +206,7 @@ struct SynthEfinixPass : public ScriptPass run("efinix_fixcarry"); run("clean"); } - + if (check_label("check")) { run("hierarchy -check"); |