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* efinix: Use dfflegalize.Marcelina Kościelnicka2020-07-062-15/+53
* Use C++11 final/override keywords.whitequark2020-06-183-8/+8
* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-192-1/+11
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-1/+0
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-022-29/+29
* synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-051-0/+1
* Merge pull request #1604 from whitequark/unify-ram-namingwhitequark2020-01-023-6/+18
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| * Harmonize BRAM/LUTRAM descriptions across all of Yosys.whitequark2020-01-013-6/+18
* | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-2/+2
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* FF should be initialized to 0Miodrag Milanovic2019-10-041-1/+3
* Add missing latch mappingMiodrag Milanovic2019-10-041-0/+12
* better handling of lut and begin/end addMiodrag Milanovic2019-09-181-4/+10
* Added simulation models for Efinix and AnlogicMiodrag Milanovic2019-09-151-2/+62
* Fix missing newline at end of fileClifford Wolf2019-08-221-1/+1
* Fix formatingMiodrag Milanovic2019-08-111-2/+2
* one bit enable signalMiodrag Milanovic2019-08-111-1/+1
* fix mixing signals on FF mappingMiodrag Milanovic2019-08-111-4/+4
* Replaced custom step with setundefMiodrag Milanovic2019-08-113-91/+1
* Fixed data widthMiodrag Milanovic2019-08-111-2/+2
* Adding new pass to fix carry chainMiodrag Milanovic2019-08-113-0/+124
* cleanupMiodrag Milanovic2019-08-111-4/+7
* Fix COMiodrag Milanovic2019-08-091-26/+24
* clock for ram trough gbufMiodrag Milanovic2019-08-041-0/+6
* Added bram supportMiodrag Milanovic2019-08-046-1/+260
* Custom step to add global clock buffersMiodrag Milanovic2019-08-034-1/+129
* Initial EFINIX supportMiodrag Milanovic2019-08-035-0/+370