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ecp5
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Author
Age
Files
Lines
*
ecp5: latches_map.v if *not* -asyncprld
Eddie Hung
2020-05-14
1
-2
/
+2
*
ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.v
Eddie Hung
2020-05-14
4
-43
/
+3
*
ecp5: fix rebase mistake
Eddie Hung
2020-05-14
1
-3
/
+3
*
ecp5: TRELLIS_FF bypass path only in async mode
Eddie Hung
2020-05-14
1
-8
/
+8
*
xilinx/ice40/ecp5: zinit requires selected wires, so select them all
Eddie Hung
2020-05-14
1
-1
/
+1
*
xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells
Eddie Hung
2020-05-14
1
-3
/
+26
*
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
Eddie Hung
2020-05-14
1
-1
/
+1
*
synth_*: no need to explicitly read +/abc9_model.v
Eddie Hung
2020-05-14
1
-1
/
+1
*
Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init"
Eddie Hung
2020-05-14
3
-220
/
+64
*
ecp5: (* abc9_flop *) gated behind YOSYS
Eddie Hung
2020-05-14
1
-0
/
+2
*
ecp5: add synth_ecp5 -dff to work with -abc9
Eddie Hung
2020-05-14
2
-12
/
+47
*
ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init
Eddie Hung
2020-05-14
3
-64
/
+220
*
ecp5: Add missing SERDES parameters
David Shah
2020-05-12
1
-0
/
+4
*
synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
Eddie Hung
2020-05-04
1
-0
/
+13
*
gowin,ecp5: remove generated files in `make clean`.
whitequark
2020-04-24
1
-0
/
+9
*
ecp5: ecp5_gsr to skip cells that don't have GSR parameter again
Eddie Hung
2020-04-22
1
-1
/
+1
*
Cleanup use of hard-coded default parameters in light of #1945
Eddie Hung
2020-04-22
2
-12
/
+6
*
ecp5: Force SIGNED ports to be 1 bit
David Shah
2020-04-16
1
-1
/
+1
*
Get rid of dffsr2dff.
Marcelina Kościelnicka
2020-04-15
1
-1
/
+0
*
Merge pull request #1603 from whitequark/ice40-ram_style
whitequark
2020-04-10
3
-1
/
+74
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\
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*
ecp5: do not map FFRAM if explicitly requested otherwise.
whitequark
2020-04-03
1
-1
/
+3
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*
ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
whitequark
2020-02-06
2
-0
/
+71
*
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kernel: big fat patch to use more ID::*, otherwise ID(*)
Eddie Hung
2020-04-02
2
-24
/
+24
*
|
Merge pull request #1716 from zeldin/ecp5_fix
N. Engelhardt
2020-03-09
1
-2
/
+0
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\
\
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*
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remove unused parameters
N. Engelhardt
2020-03-06
1
-3
/
+0
|
*
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ecp5: Add missing parameter to \$__ECP5_PDPW16KD
Marcus Comstedt
2020-02-22
1
-0
/
+1
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/
*
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synth_ecp5: use +/abc9_model.v
Eddie Hung
2020-02-27
1
-1
/
+1
*
|
ecp5: remove small LUT entries
Eddie Hung
2020-02-27
1
-24
/
+6
*
|
ecp5: deprecate abc9_{arrival,required} and *.{lut,box}
Eddie Hung
2020-02-27
7
-86
/
+120
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/
*
synth_*: call 'opt -fast' after 'techmap'
Eddie Hung
2020-02-05
1
-0
/
+1
*
Add opt_lut_ins pass. (#1673)
Marcelina Kościelnicka
2020-02-03
1
-0
/
+1
*
xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
Eddie Hung
2020-01-27
1
-77
/
+55
*
Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs
Eddie Hung
2020-01-07
4
-35
/
+31
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\
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*
Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2020-01-06
4
-4
/
+4
|
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\
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*
\
Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2020-01-02
1
-2
/
+2
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\
\
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*
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Missing character
Eddie Hung
2019-12-31
1
-1
/
+1
|
*
|
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Cleanup ecp5 boxes
Eddie Hung
2019-12-31
4
-35
/
+31
*
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|
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Re-enable &mfs for synth_{ecp5,xilinx}
Eddie Hung
2020-01-06
1
-2
/
+2
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_
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/
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/
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*
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Merge pull request #1604 from whitequark/unify-ram-naming
whitequark
2020-01-02
4
-4
/
+4
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\
\
\
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_
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/
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/
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*
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Harmonize BRAM/LUTRAM descriptions across all of Yosys.
whitequark
2020-01-01
4
-4
/
+4
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/
*
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Update doc that "-retime" calls abc with "-dff -D 1"
Eddie Hung
2019-12-30
1
-1
/
+1
*
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Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""
Eddie Hung
2019-12-30
1
-1
/
+1
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/
*
Nitpick cleanup for ecp5
Eddie Hung
2019-12-27
2
-11
/
+3
*
Revert "Optimise write_xaiger"
Eddie Hung
2019-12-20
1
-5
/
+0
*
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
Eddie Hung
2019-12-19
1
-0
/
+5
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\
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*
techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger
Eddie Hung
2019-12-06
1
-0
/
+5
*
|
Merge pull request #1563 from YosysHQ/dave/async-prld
David Shah
2019-12-18
2
-4
/
+28
|
\
\
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*
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ecp5: Add support for mapping PRLD FFs
David Shah
2019-12-07
2
-4
/
+28
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/
*
/
Fix bitwidth mismatch; suppresses iverilog warning
Eddie Hung
2019-12-11
1
-4
/
+4
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/
*
ecp5: Use new autoname pass for better cell/net names
David Shah
2019-11-15
1
-0
/
+1
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