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* abc9_ops/xaiger: further reducing Module::derive() calls by ...Eddie Hung2020-05-144-135/+121
* Cleanup; reduce Module::derive() callsEddie Hung2020-05-144-153/+164
* ecp5: latches_map.v if *not* -asyncprldEddie Hung2020-05-141-2/+2
* ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.vEddie Hung2020-05-144-43/+3
* ecp5: fix rebase mistakeEddie Hung2020-05-141-3/+3
* abc9: update to =_$abc9_flops pattern which includes whiteboxesEddie Hung2020-05-141-3/+3
* abc9_ops: update docsEddie Hung2020-05-141-11/+10
* xilinx: gate specify/attributes from iverilogEddie Hung2020-05-141-1/+3
* abc9: only do +/abc9_map if `DFFEddie Hung2020-05-142-1/+6
* abc9: rework submod -- since it won't move (* keep *) cellsEddie Hung2020-05-142-34/+29
* ecp5: TRELLIS_FF bypass path only in async modeEddie Hung2020-05-141-8/+8
* timinginfo: ignore $specify2 cells if EN is falseEddie Hung2020-05-141-0/+3
* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-143-4/+4
* abc9_ops: move assertEddie Hung2020-05-141-1/+1
* abc9: put 'aigmap' backEddie Hung2020-05-141-0/+1
* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-143-4/+198
* abc9_ops: fix bypass boxes using (* abc9_bypass *)Eddie Hung2020-05-142-14/+10
* abc9_ops: tidy up, suppress error if no boxes/holesEddie Hung2020-05-141-18/+18
* abc9_ops: -prep_delays to not insert delay box if input connection is constEddie Hung2020-05-141-0/+2
* abc9_ops: cleanup; -prep_dff -> -prep_dff_submodEddie Hung2020-05-142-22/+14
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-1411-941/+667
* abc9_ops: -reintegrate to handle $_FF_; cleanupEddie Hung2020-05-141-22/+18
* xaiger: no longer use nonstandard even/odd to designate +ve/-ve polarityEddie Hung2020-05-141-16/+5
* aiger: -xaiger to return $_FF_ flopsEddie Hung2020-05-141-15/+2
* abc9: not enough to techmap_fail on (* init=1 *), hide them using $__Eddie Hung2020-05-144-12/+48
* abc9: test to use box file instead of autoEddie Hung2020-05-143-2/+5
* abc9: restore selected_modules()Eddie Hung2020-05-141-1/+1
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-144-4/+3
* Revert "Merge pull request #1917 from YosysHQ/eddie/abc9_delay_check"Eddie Hung2020-05-141-4/+0
* abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ tooEddie Hung2020-05-147-24/+88
* kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zeroEddie Hung2020-05-141-10/+6
* abc9_ops: -prep_dff_map to error if async flop foundEddie Hung2020-05-142-9/+7
* Uncomment negative setup times; clamp to zero for connectivityEddie Hung2020-05-141-13/+29
* abc9: remove redundant wbflipEddie Hung2020-05-141-1/+0
* xaiger: always sort input/output bits by port idEddie Hung2020-05-141-12/+10
* abc9: generate $abc9_holes design instead of <name>$holesEddie Hung2020-05-143-18/+28
* abc9_ops: more robustEddie Hung2020-05-141-8/+14
* abc9: suppress warnings when no compatible + used flop boxes formedEddie Hung2020-05-143-38/+66
* xilinx: update abc9_dff testsEddie Hung2020-05-141-18/+45
* xilinx: remove no-longer-relevant testEddie Hung2020-05-141-91/+0
* aiger/xaiger: use odd for negedge clk, even for posedgeEddie Hung2020-05-142-10/+13
* abc9: cleanupEddie Hung2020-05-141-7/+11
* Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init"Eddie Hung2020-05-143-220/+64
* abc9_ops: -prep_dff_map to check $_DFF_[NP]_.Q drives module outputEddie Hung2020-05-141-1/+5
* abc9_ops: do away with '$abc9_cells' selectionEddie Hung2020-05-142-40/+30
* abc9_ops: use new 'design -delete' and 'select -unset'Eddie Hung2020-05-142-16/+7
* ecp5: (* abc9_flop *) gated behind YOSYSEddie Hung2020-05-141-0/+2
* submod: revert accidental changeEddie Hung2020-05-141-1/+1
* Revert "Merge branch 'eddie/kernel_makeblackbox' into eddie/abc9_auto_dff"Eddie Hung2020-05-141-1/+0
* xaiger: update help textEddie Hung2020-05-141-4/+4