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* ecp5: ecp5_gsr to skip cells that don't have GSR parameter againEddie Hung2020-04-221-1/+1
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* Cleanup use of hard-coded default parameters in light of #1945Eddie Hung2020-04-222-12/+6
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* ecp5: Force SIGNED ports to be 1 bitDavid Shah2020-04-161-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-1/+0
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-103-1/+74
|\ | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
| * ecp5: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-1/+3
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| * ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-062-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
* | kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-022-24/+24
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* | Merge pull request #1716 from zeldin/ecp5_fixN. Engelhardt2020-03-091-2/+0
|\ \ | | | | | | ecp5: remove unused parameter from \$__ECP5_PDPW16KD
| * | remove unused parametersN. Engelhardt2020-03-061-3/+0
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| * | ecp5: Add missing parameter to \$__ECP5_PDPW16KDMarcus Comstedt2020-02-221-0/+1
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* | synth_ecp5: use +/abc9_model.vEddie Hung2020-02-271-1/+1
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* | ecp5: remove small LUT entriesEddie Hung2020-02-271-24/+6
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* | ecp5: deprecate abc9_{arrival,required} and *.{lut,box}Eddie Hung2020-02-277-86/+120
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* synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-051-0/+1
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* Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-031-0/+1
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* xilinx/ice40/ecp5: undo permuting LUT masks in lut_mapEddie Hung2020-01-271-77/+55
| | | | Now done in read_aiger
* Merge remote-tracking branch 'origin/master' into eddie/abc9_mfsEddie Hung2020-01-074-35/+31
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| * Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-064-4/+4
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| * \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-021-2/+2
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| * | | Missing characterEddie Hung2019-12-311-1/+1
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| * | | Cleanup ecp5 boxesEddie Hung2019-12-314-35/+31
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* | | | Re-enable &mfs for synth_{ecp5,xilinx}Eddie Hung2020-01-061-2/+2
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* | | Merge pull request #1604 from whitequark/unify-ram-namingwhitequark2020-01-024-4/+4
|\ \ \ | |_|/ |/| | Harmonize BRAM/LUTRAM descriptions across all of Yosys
| * | Harmonize BRAM/LUTRAM descriptions across all of Yosys.whitequark2020-01-014-4/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit: * renames all remaining instances of "DRAM" (which is ambiguous) to "LUTRAM" (which is not), finishing the work started in the commit 698ab9be; * renames memory rule files to brams.txt/lutrams.txt; * adds/renames script labels map_bram/map_lutram; * extracts where necessary script labels map_ffram and map_gates; * adds where necessary options -nobram/-nolutram. The end result is that BRAM/LUTRAM/FFRAM aspects of every target are now consistent with each other. Per architecture: * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add :map_lutram, :map_ffram, :map_gates * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram, :map_gates * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt, rename -nodram→-nolutram (-nodram still recognized), rename :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
* | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-1/+1
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* | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-1/+1
|/ | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
* Nitpick cleanup for ecp5Eddie Hung2019-12-272-11/+3
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* Revert "Optimise write_xaiger"Eddie Hung2019-12-201-5/+0
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* Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanupEddie Hung2019-12-191-0/+5
|\ | | | | Optimise write_xaiger
| * techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaigerEddie Hung2019-12-061-0/+5
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* | Merge pull request #1563 from YosysHQ/dave/async-prldDavid Shah2019-12-182-4/+28
|\ \ | | | | | | ecp5: Add support for mapping PRLD FFs
| * | ecp5: Add support for mapping PRLD FFsDavid Shah2019-12-072-4/+28
| |/ | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* / Fix bitwidth mismatch; suppresses iverilog warningEddie Hung2019-12-111-4/+4
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* ecp5: Use new autoname pass for better cell/net namesDavid Shah2019-11-151-0/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Pass -nomfs to abc9David Shah2019-10-201-2/+2
| | | | | | Fixes #1459 Signed-off-by: David Shah <dave@ds0.me>
* Makefile: don't assume python is called `python3`Sean Cross2019-10-191-2/+2
| | | | | | | | | | | | | | | | On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross <sean@xobs.io>
* ecp5: Add ECLKBRIDGECS blackboxDavid Shah2019-10-111-0/+7
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add attrmvcp to copy syn_useioff to driving FFDavid Shah2019-10-101-0/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Set syn_useioff on IO FFs to enable packingDavid Shah2019-10-101-8/+8
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-0410-25/+25
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* Panic over. Model was elsewhere. Re-arrange for consistencyEddie Hung2019-10-041-0/+1
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* ecp5: Fix shuffle_enable portDavid Shah2019-10-011-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add support for mapping 36-bit wide PDP BRAMsDavid Shah2019-10-016-1/+183
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run onceEddie Hung2019-09-261-9/+4
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* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-057-14/+53
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| * Rename boxEddie Hung2019-09-021-1/+1
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| * Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-09-022-7/+8
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| * \ Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-307-106/+147
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| * \ \ Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-286-54/+212
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