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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-02 12:15:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-02 12:15:11 -0700 |
| commit | 696f854801619644e42f437894847ace96594a6b (patch) | |
| tree | cd0ec6901f42651b18ce8fbc2c3ef9656f7bc5d0 /techlibs/ecp5 | |
| parent | 2fa3857963376859628473123e4a36282ac14c8d (diff) | |
| download | yosys-696f854801619644e42f437894847ace96594a6b.tar.gz yosys-696f854801619644e42f437894847ace96594a6b.tar.bz2 yosys-696f854801619644e42f437894847ace96594a6b.zip | |
Rename box
Diffstat (limited to 'techlibs/ecp5')
| -rw-r--r-- | techlibs/ecp5/abc_5g.box | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box index 66ebe196a..a336b4a85 100644 --- a/techlibs/ecp5/abc_5g.box +++ b/techlibs/ecp5/abc_5g.box @@ -18,7 +18,7 @@ CCU2C 1 1 9 3 # Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram) # Outputs: DO0, DO1, DO2, DO3 # name ID w/b ins outs -$__ABC_RAM16X2_COMB 2 0 8 4 +$__ABC_DPR16X4_COMB 2 0 8 4 #A0 A1 A2 A3 RAD0 RAD1 RAD2 RAD3 0 0 0 0 141 379 275 379 |