iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Multiply using a carry-save accumulator	Clifford Wolf	2014-08-16	1	-5/+45
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*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵	Clifford Wolf	2014-08-16	1	-0/+42
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*	Changes in techmap $__alu interface	Clifford Wolf	2014-08-16	1	-17/+17
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*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15	1	-11/+11
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*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	2	-3/+3
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*	Simplified $__arraymul techmap rule	Clifford Wolf	2014-08-14	1	-7/+13
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*	RIP $safe_pmux	Clifford Wolf	2014-08-14	2	-64/+4
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*	Added techmap support for actual lookahead carry unit	Clifford Wolf	2014-08-13	1	-22/+73
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*	Preparations for lookahead ALU support in techmap.v	Clifford Wolf	2014-08-13	1	-28/+92
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*	New interface for $__alu in techmap.v	Clifford Wolf	2014-08-13	1	-129/+62
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*	Added adff2dff.v (for techmap -share_map)	Clifford Wolf	2014-08-07	2	-1/+32
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*	Implemented recursive techmap	Clifford Wolf	2014-08-03	1	-1/+1
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*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31	3	-2/+6
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*	Reorganized stdcells.v (no actual code change, just moved and indented stuff)	Clifford Wolf	2014-07-31	1	-747/+590
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*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30	1	-2/+4
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*	New techmap default rules for $shr $sshr $shl $sshl	Clifford Wolf	2014-07-30	1	-282/+62
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*	Bugfix in simlib.v for iverilog	Clifford Wolf	2014-07-29	1	-5/+6
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	2	-8/+112
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*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24	1	-10/+10
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*	Fixed simlib.v model for $mem	Clifford Wolf	2014-07-17	1	-15/+15
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*	Updated simlib to new $mem/$memwr interface	Clifford Wolf	2014-07-16	1	-30/+55
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*	Added SIMLIB_NOLUT to simlib.v	Clifford Wolf	2014-04-02	1	-0/+2
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*	Added SIMLIB_NOSR to simlib.v	Clifford Wolf	2014-04-02	1	-0/+6
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*	Added support for dlatchsr cells	Clifford Wolf	2014-03-31	2	-0/+136
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*	Merged addition of SED makefile variable from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11	1	-1/+1
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*	Fixes for improved techmap of shifts with large B inputs	Clifford Wolf	2014-03-06	1	-8/+8
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*	Strictly zero-extend unsigned A-inputs of shift operations in techmap	Clifford Wolf	2014-03-06	1	-4/+4
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*	Improved techmap of shift with wide B inputs	Clifford Wolf	2014-03-06	1	-13/+37
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*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	2	-0/+42
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*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-13/+47
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*	More changes to techlibs/common/simlib.v for LEC	Clifford Wolf	2014-01-31	1	-6/+11
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*	Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)	Clifford Wolf	2014-01-29	1	-105/+305
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*	Added $assert cell	Clifford Wolf	2014-01-19	1	-0/+15
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*	Fixed $lut simlib model for a wider range of tools	Clifford Wolf	2014-01-18	1	-10/+12
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*	More changes to simlib to make it friendlier to a wider range of tools	Clifford Wolf	2014-01-18	1	-10/+14
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*	Fixed a type in $mem model in simlib.v	Clifford Wolf	2014-01-18	1	-1/+1
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*	Removed cases of trailing comma in stdcells.v	Clifford Wolf	2014-01-18	1	-3/+3
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*	Added $bu0 cell to simlib.v	Clifford Wolf	2014-01-18	1	-0/+22
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*	Added techlibs/common/pmux2mux.v	Clifford Wolf	2014-01-17	2	-1/+26
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*	Various small cleanups in stdcells.v techmap code	Clifford Wolf	2013-12-31	1	-68/+38
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*	Added $bu0 cell (for easy correct $eq/$ne mapping)	Clifford Wolf	2013-12-28	1	-4/+10
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*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	2	-0/+86
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*	Using simplemap mappers from techmap	Clifford Wolf	2013-11-24	1	-714/+40
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*	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	Clifford Wolf	2013-11-24	4	-20/+23
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*	Install simlib in datdir	Clifford Wolf	2013-11-19	1	-0/+6
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*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11	2	-47/+43
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*	Fixed techmap of $reduce_xnor with multi-bit outputs	Clifford Wolf	2013-11-07	1	-1/+7
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*	Fixed techmap of $gt and $ge with multi-bit outputs	Clifford Wolf	2013-11-06	1	-2/+14
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*	Improved width extension with regard to undef propagation	Clifford Wolf	2013-11-06	1	-11/+11
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*	Bugfix in dffsr techmap rules	Clifford Wolf	2013-10-18	1	-8/+8
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