Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_

1 files changed, 42 insertions, 0 deletions

diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 7c8a47ddd..a2a377350 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -37,24 +37,66 @@ output Y;
 assign Y = A & B;
 endmodule
 
+module  \$_NAND_ (A, B, Y);
+input A, B;
+output Y;
+assign Y = ~(A & B);
+endmodule
+
 module  \$_OR_ (A, B, Y);
 input A, B;
 output Y;
 assign Y = A | B;
 endmodule
 
+module  \$_NOR_ (A, B, Y);
+input A, B;
+output Y;
+assign Y = ~(A | B);
+endmodule
+
 module  \$_XOR_ (A, B, Y);
 input A, B;
 output Y;
 assign Y = A ^ B;
 endmodule
 
+module  \$_XNOR_ (A, B, Y);
+input A, B;
+output Y;
+assign Y = ~(A ^ B);
+endmodule
+
 module \$_MUX_ (A, B, S, Y);
 input A, B, S;
 output Y;
 assign Y = S ? B : A;
 endmodule
 
+module  \$_AOI3_ (A, B, C, Y);
+input A, B, C;
+output Y;
+assign Y = ~((A & B) | C);
+endmodule
+
+module  \$_OAI3_ (A, B, C, Y);
+input A, B, C;
+output Y;
+assign Y = ~((A | B) & C);
+endmodule
+
+module  \$_AOI4_ (A, B, C, D, Y);
+input A, B, C, D;
+output Y;
+assign Y = ~((A & B) | (C & D));
+endmodule
+
+module  \$_OAI4_ (A, B, C, D, Y);
+input A, B, C, D;
+output Y;
+assign Y = ~((A | B) & (C | D));
+endmodule
+
 module  \$_SR_NN_ (S, R, Q);
 input S, R;
 output reg Q;