iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Added $_BUF_ cell type	Clifford Wolf	2014-10-03	1	-0/+6
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-1/+5
*	Improvements in "synth" script	Clifford Wolf	2014-09-18	1	-8/+12
*	Fixed $macc simlib model for zero-config	Clifford Wolf	2014-09-16	1	-1/+1
*	Added "synth" command	Clifford Wolf	2014-09-14	2	-0/+154
*	Using alumacc in techmap.v	Clifford Wolf	2014-09-14	1	-237/+33
*	Fixed simlib $macc model for xilinx xsim	Clifford Wolf	2014-09-08	1	-1/+15
*	Simplified $fa undef model	Clifford Wolf	2014-09-08	1	-1/+1
*	Fixes and cleanups for blackbox.v	Clifford Wolf	2014-09-08	2	-70/+73
*	Added $lcu cell type	Clifford Wolf	2014-09-08	2	-74/+31
*	Added "$fa" cell type	Clifford Wolf	2014-09-08	2	-0/+28
*	Using maccmap for $macc and $mul techmap	Clifford Wolf	2014-09-07	1	-190/+16
*	Various bug fixes (related to $macc model testing)	Clifford Wolf	2014-09-06	2	-2/+2
*	Added $macc SAT model	Clifford Wolf	2014-09-06	2	-6/+6
*	Added $macc simlib model (also use as techmap rule for now)	Clifford Wolf	2014-09-06	2	-0/+172
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	2	-34/+5
*	Undef-related fixes in simlib $alu model	Clifford Wolf	2014-09-02	1	-3/+6
*	Small bug fixes in $not, $neg, and $shiftx models	Clifford Wolf	2014-09-02	1	-3/+2
*	Fixed "test_cell -simlib all"	Clifford Wolf	2014-09-01	1	-2/+3
*	Added $lut support in test_cell, techmap, satgen	Clifford Wolf	2014-08-31	1	-0/+17
*	Added $alu cell type	Clifford Wolf	2014-08-30	2	-3/+47
*	Replaced $__alu CO/CS outputs with full-width CO output	Clifford Wolf	2014-08-30	1	-32/+28
*	Using "via_celltype" in $mul carry-save-acc implementation	Clifford Wolf	2014-08-18	1	-34/+72
*	Performance fix for new $__lcu techmap rule	Clifford Wolf	2014-08-18	1	-7/+5
*	Replaced recursive lcu scheme with bk adder	Clifford Wolf	2014-08-18	1	-61/+31
*	Multiply using a carry-save accumulator	Clifford Wolf	2014-08-16	1	-5/+45
*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...	Clifford Wolf	2014-08-16	1	-0/+42
*	Changes in techmap $__alu interface	Clifford Wolf	2014-08-16	1	-17/+17
*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15	1	-11/+11
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	2	-3/+3
*	Simplified $__arraymul techmap rule	Clifford Wolf	2014-08-14	1	-7/+13
*	RIP $safe_pmux	Clifford Wolf	2014-08-14	2	-64/+4
*	Added techmap support for actual lookahead carry unit	Clifford Wolf	2014-08-13	1	-22/+73
*	Preparations for lookahead ALU support in techmap.v	Clifford Wolf	2014-08-13	1	-28/+92
*	New interface for $__alu in techmap.v	Clifford Wolf	2014-08-13	1	-129/+62
*	Added adff2dff.v (for techmap -share_map)	Clifford Wolf	2014-08-07	2	-1/+32
*	Implemented recursive techmap	Clifford Wolf	2014-08-03	1	-1/+1
*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31	3	-2/+6
*	Reorganized stdcells.v (no actual code change, just moved and indented stuff)	Clifford Wolf	2014-07-31	1	-747/+590
*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30	1	-2/+4
*	New techmap default rules for $shr $sshr $shl $sshl	Clifford Wolf	2014-07-30	1	-282/+62
*	Bugfix in simlib.v for iverilog	Clifford Wolf	2014-07-29	1	-5/+6
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	2	-8/+112
*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24	1	-10/+10
*	Fixed simlib.v model for $mem	Clifford Wolf	2014-07-17	1	-15/+15
*	Updated simlib to new $mem/$memwr interface	Clifford Wolf	2014-07-16	1	-30/+55
*	Added SIMLIB_NOLUT to simlib.v	Clifford Wolf	2014-04-02	1	-0/+2
*	Added SIMLIB_NOSR to simlib.v	Clifford Wolf	2014-04-02	1	-0/+6
*	Added support for dlatchsr cells	Clifford Wolf	2014-03-31	2	-0/+136
*	Merged addition of SED makefile variable from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11	1	-1/+1