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author | Clifford Wolf <clifford@clifford.at> | 2014-09-16 08:19:35 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-09-16 08:19:35 +0200 |
commit | 6644e27cd4112070eca0958c19b71e97ba29a80d (patch) | |
tree | eaca39d665cac25c58024929878ca9fd050d1b5a /techlibs/common | |
parent | b86410b2ab902b587cbd8f6b14c13caf684af725 (diff) | |
download | yosys-6644e27cd4112070eca0958c19b71e97ba29a80d.tar.gz yosys-6644e27cd4112070eca0958c19b71e97ba29a80d.tar.bz2 yosys-6644e27cd4112070eca0958c19b71e97ba29a80d.zip |
Fixed $macc simlib model for zero-config
Diffstat (limited to 'techlibs/common')
-rw-r--r-- | techlibs/common/simlib.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 0ad8d14b2..2d8088adb 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -820,7 +820,7 @@ function integer my_clog2; end endfunction -localparam integer num_bits = CONFIG[3:0]; +localparam integer num_bits = CONFIG[3:0] > 0 ? CONFIG[3:0] : 1; localparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits); localparam integer num_abits = my_clog2(A_WIDTH) > 0 ? my_clog2(A_WIDTH) : 1; |