aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/common
Commit message (Collapse)AuthorAgeFilesLines
* Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-patternclairexen2020-08-201-1/+1
|\ | | | | techmap: Add support for [] wildcards in techmap_celltype.
| * techmap: Add support for [] wildcards in techmap_celltype.Marcelina Kościelnicka2020-08-021-1/+1
| | | | | | | | Fixes #1826.
* | Respect \A_SIGNED for $shiftXiretza2020-08-182-6/+16
| | | | | | | | | | | | This reflects the behaviour of $shr/$shl, which sign-extend their A operands to the size of their output, then do a logical shift (shift in 0-bits).
* | Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-3/+3
|/
* simcells: Fix reset polarity for $_DLATCH_???_ cells.Marcelina Kościelnicka2020-06-302-5/+5
|
* Add new FF types to simplemap.Marcelina Kościelnicka2020-06-231-1/+1
|
* Add new builtin FF typesMarcelina Kościelnicka2020-06-233-0/+2293
| | | | | | | | | | | | | | The new types include: - FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`) - FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`) - FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`) - FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`) - FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`) - latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`) The new FF types are not actually used anywhere yet (this is left for future commits).
* Use C++11 final/override keywords.whitequark2020-06-182-8/+8
|
* Do not optimize away FFs in "prep" and Verific fron-endClaire Wolf2020-06-091-2/+2
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-1/+1
|\ | | | | abc9: -dff improvements
| * abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_Eddie Hung2020-05-291-1/+1
| |
* | Add flooring division operatorXiretza2020-05-282-0/+71
| | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
* | Add flooring modulo operatorXiretza2020-05-282-3/+124
|/ | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-196-23/+88
| | | | Fixes #2058.
* abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_Eddie Hung2020-05-142-14/+2
| | | | instead of moving them to $__ prefix
* abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove itEddie Hung2020-05-142-5/+4
|
* abc9_ops/xaiger: further reducing Module::derive() calls by ...Eddie Hung2020-05-142-7/+5
| | | | replacing _all_ (* abc9_box *) instantiations with their derived types
* Cleanup; reduce Module::derive() callsEddie Hung2020-05-142-4/+4
|
* abc9: only do +/abc9_map if `DFFEddie Hung2020-05-141-0/+2
|
* abc9: not enough to techmap_fail on (* init=1 *), hide them using $__Eddie Hung2020-05-142-10/+26
|
* abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ tooEddie Hung2020-05-144-0/+55
|
* abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxesEddie Hung2020-05-141-3/+0
|
* techlibs/common: more robustness when *_WIDTH = 0Eddie Hung2020-05-052-7/+30
|
* Fix the truth table for $_SR_* cells.Marcelina Kościelnicka2020-04-153-26/+21
| | | | | | | | This brings the documented behavior for these cells in line with $_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S. The models were already reflecting that behavior. Also get rid of sim-synth mismatch in the models while we're at it.
* Merge pull request #1648 from YosysHQ/eddie/cmp2lcuEddie Hung2020-04-034-11/+120
|\ | | | | "techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
| * cmp2lcu: rename _90_lcu_cmp -> _80_lcu_cmpEddie Hung2020-04-031-1/+1
| |
| * cmp2lcu: fail if `LUT_WIDTH < 2Eddie Hung2020-04-031-1/+1
| |
| * synth: only techmap cmp2{lut,lcu} if -lutEddie Hung2020-04-031-1/+1
| |
| * synth: use +/cmp2lcu.v in generic 'synth' tooEddie Hung2020-04-031-2/+2
| |
| * Cleanup +/cmp2lut.vEddie Hung2020-04-031-8/+0
| |
| * +/cmp2lcu.v to work efficiently for fully/partially constant inputsEddie Hung2020-04-031-33/+42
| |
| * Refactor +/cmp2lcu.v into recursive techmapEddie Hung2020-04-031-38/+65
| |
| * CleanupEddie Hung2020-04-031-31/+28
| |
| * Cleanup cmp2lcu.vEddie Hung2020-04-031-16/+16
| |
| * techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcuEddie Hung2020-04-032-0/+84
| |
| * cmp2lut: comment out unused since 362f4f9Eddie Hung2020-04-031-8/+8
| |
* | simcells.v: Generate the fine FF cell types by a python script.Marcin Kościelnicki2020-04-022-19/+270
|/ | | | | | This makes adding more FF types in the future much more manageable. Fixes #1824.
* Fix invalid verilog syntaxMiodrag Milanovic2020-03-141-1/+1
|
* Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabcN. Engelhardt2020-03-031-2/+17
|\ | | | | Add -flowmap option to `synth{,_ice40}`
| * Add -flowmap to synth and synth_ice40Dan Ravensloft2020-02-281-2/+17
| |
* | Create +/abc9_model.v for $__ABC9_{DELAY,FF_}Eddie Hung2020-02-272-0/+11
|/
* techmap: fix shiftx2mux decompositionEddie Hung2020-02-071-8/+6
|
* shiftx2mux: fix select out of boundsEddie Hung2020-02-051-1/+2
|
* Merge remote-tracking branch 'origin/master' into eddie/shiftx2muxEddie Hung2020-02-052-2/+0
|\
| * abc9_ops: -write_box is empty, output a dummy box to prevent ABC errorEddie Hung2020-01-152-2/+0
| |
* | Explicitly create separate $mux cellsEddie Hung2020-01-211-2/+2
| |
* | Fix tests -- when Y_WIDTH is non-pow-2Eddie Hung2020-01-211-3/+4
| |
* | Move from +/shiftx2mux.v into +/techmap.v; cleanupEddie Hung2020-01-213-73/+69
| |
* | New techmap +/shiftx2mux.v which decomposes LSB first; better for ABCEddie Hung2020-01-212-0/+39
|/
* Do not map $eq and $ne in cmp2lut, only proper arithmetic cmpClifford Wolf2019-11-111-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-03 17:16:49 +0000