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| author | Xiretza <xiretza@xiretza.xyz> | 2020-07-03 13:13:21 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-08-18 19:36:24 +0200 |
| commit | 928fd40c2ebc8b83b76c02d80d751d2531341d9d (patch) | |
| tree | 7bc53f51a0c374c33549c07bf952eb01716bd20e /techlibs/common | |
| parent | 22765ef0a5ff5af9f6efae9b5443afa7bccfb4e5 (diff) | |
| download | yosys-928fd40c2ebc8b83b76c02d80d751d2531341d9d.tar.gz yosys-928fd40c2ebc8b83b76c02d80d751d2531341d9d.tar.bz2 yosys-928fd40c2ebc8b83b76c02d80d751d2531341d9d.zip | |
Respect \A_SIGNED for $shift
This reflects the behaviour of $shr/$shl, which sign-extend their A
operands to the size of their output, then do a logical shift (shift in
0-bits).
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/simlib.v | 16 | ||||
| -rw-r--r-- | techlibs/common/techmap.v | 6 |
2 files changed, 16 insertions, 6 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 2660e6f15..e94884025 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -480,10 +480,18 @@ input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; generate - if (B_SIGNED) begin:BLOCK1 - assign Y = $signed(B) < 0 ? A << -B : A >> B; - end else begin:BLOCK2 - assign Y = A >> B; + if (A_SIGNED) begin:BLOCK1 + if (B_SIGNED) begin:BLOCK2 + assign Y = $signed(B) < 0 ? $signed(A) << -B : $signed(A) >> B; + end else begin:BLOCK3 + assign Y = $signed(A) >> B; + end + end else begin:BLOCK4 + if (B_SIGNED) begin:BLOCK5 + assign Y = $signed(B) < 0 ? A << -B : A >> B; + end else begin:BLOCK6 + assign Y = A >> B; + end end endgenerate diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 9607302b7..03c27d49d 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -141,6 +141,7 @@ module _90_shift_shiftx (A, B, Y); parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0; localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx; + wire a_padding = _TECHMAP_CELLTYPE_ == "$shiftx" ? extbit : (A_SIGNED ? A[A_WIDTH-1] : 1'b0); generate `ifndef NO_LSB_FIRST_SHIFT_SHIFTX @@ -160,7 +161,7 @@ module _90_shift_shiftx (A, B, Y); localparam entries = (A_WIDTH+Y_WIDTH-1)/Y_WIDTH2; localparam len = Y_WIDTH2 * ((entries+1)/2); wire [len-1:0] AA; - wire [(A_WIDTH+Y_WIDTH2+Y_WIDTH-1)-1:0] Apad = {{(Y_WIDTH2+Y_WIDTH-1){extbit}}, A}; + wire [(A_WIDTH+Y_WIDTH2+Y_WIDTH-1)-1:0] Apad = {{(Y_WIDTH2+Y_WIDTH-1){a_padding}}, A}; genvar i; for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2) assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? Apad[i+Y_WIDTH2 +: Y_WIDTH2] : Apad[i +: Y_WIDTH2]; @@ -187,7 +188,8 @@ module _90_shift_shiftx (A, B, Y); always @* begin overflow = 0; buffer = {WIDTH{extbit}}; - buffer[`MAX(A_WIDTH, Y_WIDTH)-1:0] = A; + buffer[Y_WIDTH-1:0] = {Y_WIDTH{a_padding}}; + buffer[A_WIDTH-1:0] = A; if (B_WIDTH > BB_WIDTH) begin if (B_SIGNED) begin |