iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs	Clifford Wolf	2019-08-06	1	-0/+19
*	Fix typo.	whitequark	2018-12-05	1	-2/+2
*	Add $_ANDNOT_ and $_ORNOT_ gates	Clifford Wolf	2017-05-17	1	-0/+38
*	Added $global_clock verilog syntax support for creating $ff cells	Clifford Wolf	2016-10-14	1	-0/+17
*	Progress in cell library documentation	Clifford Wolf	2016-02-01	1	-0/+238
*	Progress on cell help messages	Clifford Wolf	2015-10-20	1	-18/+114
*	Progress on cell help messages	Clifford Wolf	2015-10-17	1	-50/+94
*	Added more cell descriptions	Clifford Wolf	2015-10-14	1	-0/+85
*	Added first help messages for cell types	Clifford Wolf	2015-10-14	1	-0/+250
*	Added $tribuf and $_TBUF_ sim models	Clifford Wolf	2015-08-16	1	-0/+6
*	Another block of spelling fixes	Larry Doolittle	2015-08-14	1	-1/+1
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-2/+2
*	Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types	Clifford Wolf	2015-04-05	1	-0/+29
*	Added $_DFFE_??_ cell types	Clifford Wolf	2014-12-08	1	-0/+32
*	Added $_BUF_ cell type	Clifford Wolf	2014-10-03	1	-0/+6
*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...	Clifford Wolf	2014-08-16	1	-0/+42
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-2/+2
*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31	1	-1/+1
*	Added support for dlatchsr cells	Clifford Wolf	2014-03-31	1	-0/+104
*	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	Clifford Wolf	2013-11-24	1	-0/+327