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| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2015-08-14 13:23:01 -0700 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-08-14 23:27:05 +0200 |
| commit | 6c00704a5ef09be46b1f05e2be477e493f37dd38 (patch) | |
| tree | a64fb142c62fd5cd49a9928b5125ea4e133f4471 /techlibs/common/simcells.v | |
| parent | 022f570563d8b067e9638bc91bbd168f4c5cb817 (diff) | |
| download | yosys-6c00704a5ef09be46b1f05e2be477e493f37dd38.tar.gz yosys-6c00704a5ef09be46b1f05e2be477e493f37dd38.tar.bz2 yosys-6c00704a5ef09be46b1f05e2be477e493f37dd38.zip | |
Another block of spelling fixes
Smaller this time
Diffstat (limited to 'techlibs/common/simcells.v')
| -rw-r--r-- | techlibs/common/simcells.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index 669706209..9a820f71c 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -19,7 +19,7 @@ * * The internal logic cell simulation library. * - * This verilog library contains simple simulation models for the internal + * This Verilog library contains simple simulation models for the internal * logic cells ($_NOT_ , $_AND_ , ...) that are generated by the default technology * mapper (see "techmap.v" in this directory) and expected by the "abc" pass. * |