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author | Clifford Wolf <clifford@clifford.at> | 2016-10-14 12:33:56 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2016-10-14 12:33:56 +0200 |
commit | 53655d173b2928328061c8440cc993508e951e1f (patch) | |
tree | 87c12bdeb1a7cde96569efd1da18bee909b2f115 /techlibs/common/simcells.v | |
parent | ffbb4e992e5312d8feafcc1c6c850ea06c3e09b2 (diff) | |
download | yosys-53655d173b2928328061c8440cc993508e951e1f.tar.gz yosys-53655d173b2928328061c8440cc993508e951e1f.tar.bz2 yosys-53655d173b2928328061c8440cc993508e951e1f.zip |
Added $global_clock verilog syntax support for creating $ff cells
Diffstat (limited to 'techlibs/common/simcells.v')
-rw-r--r-- | techlibs/common/simcells.v | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index c4f170a3c..e770c5453 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -495,6 +495,23 @@ always @(posedge S, posedge R) begin end endmodule +`ifdef SIMCELLS_FF +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $_FF_ (D, Q) +//- +//- A D-type flip-flop that is clocked from the implicit global clock. (This cell +//- type is usually only used in netlists for formal verification.) +//- +module \$_FF_ (D, Q); +input D; +output reg Q; +always @($global_clock) begin + Q <= D; +end +endmodule +`endif + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| //- //- $_DFF_N_ (D, C, Q) |