| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix files with CRLF line endings | Claire Xenia Wolf | 2021-06-09 | 1 | -318/+318 |
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| * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 1 | -2/+2 |
| | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g; | ||||
| * | verilog: significant block scoping improvements | Zachary Snow | 2021-01-31 | 1 | -22/+26 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493 | ||||
| * | Add force_downto and force_upto wire attributes. | Marcelina Kościelnicka | 2020-05-19 | 1 | -0/+18 |
| | | | | | Fixes #2058. | ||||
| * | Missing (* mul2dsp *) for sliceB | Eddie Hung | 2019-09-27 | 1 | -2/+2 |
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| * | Stop trying to be too smart by prematurely optimising | Eddie Hung | 2019-09-26 | 1 | -34/+6 |
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| * | mul2dsp.v slice names | Eddie Hung | 2019-09-25 | 1 | -5/+5 |
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| * | Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit | Eddie Hung | 2019-09-25 | 1 | -3/+1 |
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| * | Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul" | Eddie Hung | 2019-09-25 | 1 | -2/+6 |
| | | | | | This reverts commit 234738b103d4f2b3d937ed928fd89bc4e31627f1. | ||||
| * | Revert "No need for $__mul anymore?" | Eddie Hung | 2019-09-25 | 1 | -8/+8 |
| | | | | | This reverts commit 1d875ac76a354f654f28b9632d83f6b43542e827. | ||||
| * | Remove _TECHMAP_CELLTYPE_ check since all $mul | Eddie Hung | 2019-09-25 | 1 | -6/+2 |
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| * | No need for $__mul anymore? | Eddie Hung | 2019-09-25 | 1 | -8/+8 |
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| * | Fix signedness bug | Eddie Hung | 2019-09-20 | 1 | -2/+2 |
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| * | Be sensitive to signedness | Eddie Hung | 2019-09-10 | 1 | -20/+21 |
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| * | Really get rid of 'opt_expr -fine' by being explicit | Eddie Hung | 2019-09-10 | 1 | -6/+33 |
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| * | Only swap ports if $mul and not $__mul | Eddie Hung | 2019-08-13 | 1 | -1/+1 |
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| * | Add DSP_A_MAXWIDTH_PARTIAL, refactor | Eddie Hung | 2019-08-13 | 1 | -144/+110 |
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| * | Trim Y_WIDTH | Eddie Hung | 2019-08-01 | 1 | -5/+3 |
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| * | Add DSP_SIGNEDONLY back | Eddie Hung | 2019-08-01 | 1 | -0/+16 |
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| * | DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH | Eddie Hung | 2019-08-01 | 1 | -4/+11 |
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| * | Revert "Do not do sign extension in techmap; let packer do it" | Eddie Hung | 2019-08-01 | 1 | -5/+14 |
| | | | | | This reverts commit 595a8f032f1e9db385959f92a4a414a40de291fd. | ||||
| * | Fix B_WIDTH > DSP_B_MAXWIDTH case | Eddie Hung | 2019-08-01 | 1 | -32/+14 |
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| * | Do not compute sign bit if result is zero | Eddie Hung | 2019-07-31 | 1 | -1/+2 |
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| * | For signed multipliers, compute sign bit separately... | Eddie Hung | 2019-07-31 | 1 | -23/+42 |
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| * | Fix spacing | Eddie Hung | 2019-07-26 | 1 | -3/+3 |
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| * | Add copyright header, comment on cascade | Eddie Hung | 2019-07-24 | 1 | -4/+34 |
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| * | Typo for Y_WIDTH | Eddie Hung | 2019-07-23 | 1 | -1/+1 |
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| * | Use minimum sized width wires | Eddie Hung | 2019-07-22 | 1 | -7/+13 |
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| * | Indirection via $__soft_mul | Eddie Hung | 2019-07-19 | 1 | -9/+9 |
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| * | Do not do sign extension in techmap; let packer do it | Eddie Hung | 2019-07-19 | 1 | -14/+5 |
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| * | Do not $mul -> $__mul if A and B are less than maxwidth | Eddie Hung | 2019-07-19 | 1 | -1/+3 |
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| * | Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too | Eddie Hung | 2019-07-19 | 1 | -28/+68 |
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| * | Merge branch 'xc7dsp' into ice40dsp | Eddie Hung | 2019-07-19 | 1 | -1/+1 |
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| | * | Fix typo in B | Eddie Hung | 2019-07-19 | 1 | -1/+1 |
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| * | | Use sign_headroom instead | Eddie Hung | 2019-07-19 | 1 | -4/+4 |
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| * | | Do not define `DSP_SIGNEDONLY macro if no exists | Eddie Hung | 2019-07-18 | 1 | -4/+3 |
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| * | | mul2dsp to create cells that can be interchanged with $mul | Eddie Hung | 2019-07-18 | 1 | -1/+7 |
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| * | Make consistent | Eddie Hung | 2019-07-18 | 1 | -1/+2 |
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| * | Fix signed multiplier decomposition | Eddie Hung | 2019-07-18 | 1 | -29/+36 |
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| * | Working for unsigned | Eddie Hung | 2019-07-18 | 1 | -52/+28 |
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| * | Cleanup | Eddie Hung | 2019-07-18 | 1 | -70/+58 |
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| * | mul2dsp: Lower partial products always have unsigned inputs | David Shah | 2019-07-18 | 1 | -31/+41 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | Fix mul2dsp signedness | Eddie Hung | 2019-07-17 | 1 | -42/+38 |
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| * | A_SIGNED == B_SIGNED so flip both | Eddie Hung | 2019-07-17 | 1 | -21/+12 |
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| * | Add DSP_{A,B}_SIGNEDONLY macro | Eddie Hung | 2019-07-16 | 1 | -11/+40 |
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| * | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-07-16 | 1 | -22/+26 |
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| | * | mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH | David Shah | 2019-07-16 | 1 | -18/+22 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | mul2dsp: Fix indentation | David Shah | 2019-07-16 | 1 | -7/+7 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | Do not swap if equals | Eddie Hung | 2019-07-15 | 1 | -1/+1 |
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| * | | OUT port to Y in generic DSP | Eddie Hung | 2019-07-15 | 1 | -1/+1 |
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index : iCE40/yosys | |
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