aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/common/mul2dsp.v
Commit message (Collapse)AuthorAgeFilesLines
* Missing (* mul2dsp *) for sliceBEddie Hung2019-09-271-2/+2
|
* Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-261-34/+6
|
* mul2dsp.v slice namesEddie Hung2019-09-251-5/+5
|
* Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicitEddie Hung2019-09-251-3/+1
|
* Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"Eddie Hung2019-09-251-2/+6
| | | | This reverts commit 234738b103d4f2b3d937ed928fd89bc4e31627f1.
* Revert "No need for $__mul anymore?"Eddie Hung2019-09-251-8/+8
| | | | This reverts commit 1d875ac76a354f654f28b9632d83f6b43542e827.
* Remove _TECHMAP_CELLTYPE_ check since all $mulEddie Hung2019-09-251-6/+2
|
* No need for $__mul anymore?Eddie Hung2019-09-251-8/+8
|
* Fix signedness bugEddie Hung2019-09-201-2/+2
|
* Be sensitive to signednessEddie Hung2019-09-101-20/+21
|
* Really get rid of 'opt_expr -fine' by being explicitEddie Hung2019-09-101-6/+33
|
* Only swap ports if $mul and not $__mulEddie Hung2019-08-131-1/+1
|
* Add DSP_A_MAXWIDTH_PARTIAL, refactorEddie Hung2019-08-131-144/+110
|
* Trim Y_WIDTHEddie Hung2019-08-011-5/+3
|
* Add DSP_SIGNEDONLY backEddie Hung2019-08-011-0/+16
|
* DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTHEddie Hung2019-08-011-4/+11
|
* Revert "Do not do sign extension in techmap; let packer do it"Eddie Hung2019-08-011-5/+14
| | | | This reverts commit 595a8f032f1e9db385959f92a4a414a40de291fd.
* Fix B_WIDTH > DSP_B_MAXWIDTH caseEddie Hung2019-08-011-32/+14
|
* Do not compute sign bit if result is zeroEddie Hung2019-07-311-1/+2
|
* For signed multipliers, compute sign bit separately...Eddie Hung2019-07-311-23/+42
|
* Fix spacingEddie Hung2019-07-261-3/+3
|
* Add copyright header, comment on cascadeEddie Hung2019-07-241-4/+34
|
* Typo for Y_WIDTHEddie Hung2019-07-231-1/+1
|
* Use minimum sized width wiresEddie Hung2019-07-221-7/+13
|
* Indirection via $__soft_mulEddie Hung2019-07-191-9/+9
|
* Do not do sign extension in techmap; let packer do itEddie Hung2019-07-191-14/+5
|
* Do not $mul -> $__mul if A and B are less than maxwidthEddie Hung2019-07-191-1/+3
|
* Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 tooEddie Hung2019-07-191-28/+68
|
* Merge branch 'xc7dsp' into ice40dspEddie Hung2019-07-191-1/+1
|\
| * Fix typo in BEddie Hung2019-07-191-1/+1
| |
* | Use sign_headroom insteadEddie Hung2019-07-191-4/+4
| |
* | Do not define `DSP_SIGNEDONLY macro if no existsEddie Hung2019-07-181-4/+3
| |
* | mul2dsp to create cells that can be interchanged with $mulEddie Hung2019-07-181-1/+7
|/
* Make consistentEddie Hung2019-07-181-1/+2
|
* Fix signed multiplier decompositionEddie Hung2019-07-181-29/+36
|
* Working for unsignedEddie Hung2019-07-181-52/+28
|
* CleanupEddie Hung2019-07-181-70/+58
|
* mul2dsp: Lower partial products always have unsigned inputsDavid Shah2019-07-181-31/+41
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix mul2dsp signednessEddie Hung2019-07-171-42/+38
|
* A_SIGNED == B_SIGNED so flip bothEddie Hung2019-07-171-21/+12
|
* Add DSP_{A,B}_SIGNEDONLY macroEddie Hung2019-07-161-11/+40
|
* Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-161-22/+26
|\
| * mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTHDavid Shah2019-07-161-18/+22
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * mul2dsp: Fix indentationDavid Shah2019-07-161-7/+7
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Do not swap if equalsEddie Hung2019-07-151-1/+1
| |
* | OUT port to Y in generic DSPEddie Hung2019-07-151-1/+1
|/
* Only swap if B_WIDTH > A_WIDTHEddie Hung2019-07-151-1/+1
|
* Tidy upEddie Hung2019-07-151-39/+26
|
* mul2dsp: Fix typoDavid Shah2019-07-081-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Add mul2dsp multiplier splitting rule and ECP5 mappingDavid Shah2019-07-081-0/+237
Signed-off-by: David Shah <dave@ds0.me>