| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | Replace `std::set`s using custom comparators with `pool`. | Alberto Gonzalez | 2020-05-14 | 1 | -4/+4 | |
| | | | | | | | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com> | |||||
| | * | | techmap: prefix special wires with backslash for use as IdString | Eddie Hung | 2020-05-14 | 1 | -11/+12 | |
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| | * | | Further clean up `passes/techmap/techmap.cc`. | Alberto Gonzalez | 2020-05-14 | 1 | -5/+6 | |
| | | | | | | | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com> | |||||
| | * | | Use `emplace()` for more efficient insertion into various `dict`s. | Alberto Gonzalez | 2020-05-14 | 1 | -8/+8 | |
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| | * | | Build constant bits directly rather than constructing an object and copying ↵ | Alberto Gonzalez | 2020-05-14 | 1 | -2/+5 | |
| | | | | | | | | | | | | | its bits. | |||||
| | * | | Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`. | Alberto Gonzalez | 2020-05-14 | 1 | -2/+2 | |
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| | * | | Use `emplace()` rather than `insert()`. | Alberto Gonzalez | 2020-05-14 | 1 | -1/+1 | |
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| | * | | Clean up pseudo-private member usage and ensure range iteration uses ↵ | Alberto Gonzalez | 2020-05-14 | 1 | -17/+17 | |
| | | | | | | | | | | | | | references where possible to avoid unnecessary copies. | |||||
| | * | | Clean up extraneous buffer. | Alberto Gonzalez | 2020-05-14 | 1 | -5/+2 | |
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| | * | | Replace `std::map` with `dict` for `unique_bit_id`. | Alberto Gonzalez | 2020-05-14 | 1 | -1/+1 | |
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| | * | | Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and ↵ | Alberto Gonzalez | 2020-05-14 | 1 | -3/+3 | |
| | | | | | | | | | | | | | `cellbits_to_tplbits`. | |||||
| | * | | Replace `std::map` with `dict` for `connbits_map`, `cell_to_inbit`, and ↵ | Alberto Gonzalez | 2020-05-14 | 1 | -3/+3 | |
| | | | | | | | | | | | | | `outbit_to_cell`. | |||||
| | * | | Replace `std::map` with `dict` for `TechmapWires` type. | Alberto Gonzalez | 2020-05-14 | 1 | -1/+1 | |
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| | * | | Replace `std::map` with `dict` for `celltypeMap`. | Alberto Gonzalez | 2020-05-14 | 1 | -3/+3 | |
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| | * | | Replace `std::set` with `pool` for `handled_cells` and `techmap_wire_names`. | Alberto Gonzalez | 2020-05-14 | 1 | -4/+4 | |
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| | * | | Replace `std::map` with `dict` for `positional_ports`. | Alberto Gonzalez | 2020-05-14 | 1 | -1/+1 | |
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| | * | | Add specialized `hash()` for type `dict` and use a `dict` instead of a ↵ | Alberto Gonzalez | 2020-05-14 | 1 | -4/+4 | |
| | | | | | | | | | | | | | `std::map` for `techmap_cache` and `techmap_do_cache`. | |||||
| | * | | Replace `std::map` with `dict` for `simplemap_mappers`. | Alberto Gonzalez | 2020-05-14 | 3 | -5/+5 | |
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| | * | | Use `nullptr` instead of `NULL` in `passes/techmap/techmap.cc`. | Alberto Gonzalez | 2020-05-14 | 1 | -10/+10 | |
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| | * | | Replace `std::string` and `RTLIL::IdString` with `IdString` in ↵ | Alberto Gonzalez | 2020-05-14 | 1 | -21/+21 | |
| | | | | | | | | | | | | | | | | | | | `passes/techmap/techmap.cc`. Co-Authored-By: Eddie Hung <eddie@fpgeh.com> | |||||
| | * | | Do not modify design modules while iterating over `modules()`. | Alberto Gonzalez | 2020-05-14 | 1 | -1/+4 | |
| | | | | | | | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com> | |||||
| | * | | Clean up pseudo-private member usage, superfluous `std::vector` ↵ | Alberto Gonzalez | 2020-05-14 | 1 | -76/+70 | |
| | | | | | | | | | | | | | instantiation, and `RTLIL::id2cstr()` usage in `passes/techmap/techmap.cc`. | |||||
| * | | | Merge pull request #2081 from YosysHQ/eddie/blackbox_ast | Eddie Hung | 2020-05-30 | 1 | -25/+1 | |
| |\ \ \ | | | | | | | | | blackbox: use Module::makeblackbox() method | |||||
| | * | | | blackbox: re-use existing Module::makeblackbox() method | Eddie Hung | 2020-05-25 | 1 | -25/+1 | |
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| * | | | Merge pull request #2018 from boqwxp/qbfsat-timeout | clairexen | 2020-05-30 | 1 | -13/+53 | |
| |\ \ \ | | | | | | | | | smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4. | |||||
| | * | | | smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, ↵ | Alberto Gonzalez | 2020-05-25 | 1 | -13/+53 | |
| | | | | | | | | | | | | | | | | | and CVC4. | |||||
| * | | | | Merge pull request #1885 from Xiretza/mod-rem-cells | clairexen | 2020-05-29 | 7 | -15/+65 | |
| |\ \ \ \ | | | | | | | | | | | Fix modulo/remainder semantics | |||||
| | * | | | | Add flooring division operator | Xiretza | 2020-05-28 | 7 | -13/+36 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor. | |||||
| | * | | | | Add flooring modulo operator | Xiretza | 2020-05-28 | 7 | -12/+39 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor. | |||||
| * | | | | | Merge pull request #2017 from boqwxp/qbfsat-cvc4 | clairexen | 2020-05-29 | 1 | -2/+6 | |
| |\ \ \ \ \ | | |/ / / | |/| | | | qbfsat: Add support for CVC4. | |||||
| | * | | | | qbfsat: Add support for CVC4. | Alberto Gonzalez | 2020-05-25 | 1 | -2/+6 | |
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| * | | | | | Merge pull request #2016 from boqwxp/qbfsat-yices | clairexen | 2020-05-29 | 1 | -20/+47 | |
| |\| | | | | |/ / / |/| | | | qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default. | |||||
| | * | | | qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices ↵ | Alberto Gonzalez | 2020-05-25 | 1 | -20/+47 | |
| | |/ / | | | | | | | | | | | | | | | | the default. Ensures that "BV" is the logic whenever solving an exists-forall problem with Yices, moves the "(set-logic ...)" directive above any non-info line, sets the `ef-max-iters` parameter to a very high number when using Yices in exists-forall mode so as not to prematurely abandon difficult problems, and does not provide the incompatible "--incremental" Yices argument when in exists-forall mode. | |||||
| * | | | Merge pull request #2095 from rswarbrick/hier-typo | whitequark | 2020-05-28 | 1 | -2/+2 | |
| |\ \ \ | | | | | | | | | Fix small typos in documentation for hierarchy command | |||||
| | * | | | Fix small typos in documentation for hierarchy command | Rupert Swarbrick | 2020-05-28 | 1 | -2/+2 | |
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| * | | | printattrs: Simplify `get_indent_str()`. | Alberto Gonzalez | 2020-05-28 | 1 | -3/+1 | |
| | | | | | | | | | | | | | Co-Authored-By: Xiretza <xiretza@xiretza.xyz> | |||||
| * | | | printattrs: Refactor indentation string building for clarity. | Alberto Gonzalez | 2020-05-27 | 1 | -5/+11 | |
| | | | | | | | | | | | | | Co-Authored-By: whitequark <whitequark@whitequark.org> | |||||
| * | | | printattrs: Use `flags` to pretty-print the `RTLIL::Const` appropriately. | Alberto Gonzalez | 2020-05-27 | 1 | -8/+15 | |
| | | | | | | | | | | | | | Co-Authored-By: whitequark <whitequark@whitequark.org> | |||||
| * | | | misc: Add `printattrs` command. | Alberto Gonzalez | 2020-05-27 | 2 | -0/+80 | |
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| * | | Merge pull request #2015 from boqwxp/qbfsat-bisection | clairexen | 2020-05-25 | 1 | -98/+207 | |
| |\ \ | | | | | | | qbfsat: Add an iterative bisection optimization method and make it the default. | |||||
| | * | | qbfsat: Remove cruft inadvertently left untouched in commit ↵ | Alberto Gonzalez | 2020-05-23 | 1 | -11/+0 | |
| | | | | | | | | | | | | | 86fc49a9d60f9ad4cdeec93663e7245a9fdf60c6. | |||||
| | * | | qbfsat: Add bisection mode and make it the default. | Alberto Gonzalez | 2020-05-23 | 1 | -87/+207 | |
| | |/ | | | | | | | Also adds `-nooptimize` and reorganizes `qbfsat.cc` a bit. | |||||
| * | | abc9_ops: update comment | Eddie Hung | 2020-05-21 | 1 | -1/+1 | |
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| * | | Merge pull request #2059 from boqwxp/logger-vector-to-dict | Miodrag Milanović | 2020-05-21 | 1 | -33/+6 | |
| |\ \ | | | | | | | log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique. | |||||
| | * | | log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, ↵ | Alberto Gonzalez | 2020-05-15 | 1 | -33/+6 | |
| | | | | | | | | | | | | | warning, log}` to better express the intent that each element is unique. | |||||
| * | | | Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff | Eddie Hung | 2020-05-18 | 2 | -372/+895 | |
| |\ \ \ | |/ / |/| | | abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *) | |||||
| | * | | abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_ | Eddie Hung | 2020-05-14 | 1 | -3/+3 | |
| | | | | | | | | | | | | | instead of moving them to $__ prefix | |||||
| | * | | abc9_ops: -prep_hier to create unmap module that removes Q's (* init *) | Eddie Hung | 2020-05-14 | 1 | -4/+6 | |
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| | * | | abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it | Eddie Hung | 2020-05-14 | 1 | -17/+1 | |
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| | * | | Fix broken test when ignoring abc9_flop with init == 1'b1 | Eddie Hung | 2020-05-14 | 1 | -3/+0 | |
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