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Files
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-27
1
-7
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+3
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Do not replace constants with same wire
Eddie Hung
2019-11-27
1
-7
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+3
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-27
1
-47
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+71
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Cleanup
Eddie Hung
2019-11-27
1
-5
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+3
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Check for nullptr
Eddie Hung
2019-11-27
1
-1
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+1
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Stray log_dump
Eddie Hung
2019-11-27
1
-1
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+0
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Revert "submod to bitty rather bussy, for bussy wires used as input and output"
Eddie Hung
2019-11-27
1
-40
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+71
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Promote output wires in sigmap so that can be detected
Eddie Hung
2019-11-26
1
-8
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+4
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Fix submod -hidden
Eddie Hung
2019-11-26
1
-5
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+6
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Add -hidden option to submod
Eddie Hung
2019-11-26
1
-11
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+25
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Update docs with bullet points
Eddie Hung
2019-11-26
1
-10
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+9
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Move \init from source wire to submod if output port
Eddie Hung
2019-11-25
1
-0
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+7
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Fix submod -hidden
Eddie Hung
2019-11-26
1
-5
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+6
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clkpart to use 'submod -hidden'
Eddie Hung
2019-11-26
1
-1
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+1
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Add -hidden option to submod
Eddie Hung
2019-11-26
1
-20
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+40
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Fix debug
Eddie Hung
2019-11-25
1
-3
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+3
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-11-25
1
-0
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+41
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clkbufmap: Add support for inverters in clock path.
Marcin Kościelnicki
2019-11-25
1
-0
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+41
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abc9 to contain time call
Eddie Hung
2019-11-25
1
-1
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+1
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abc9 to no longer to clock partitioning, operate on whole modules only
Eddie Hung
2019-11-25
1
-139
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+32
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clkpart to analyse async flops too
Eddie Hung
2019-11-25
1
-0
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+8
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Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung
2019-11-23
1
-2
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+3
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More oopsies
Eddie Hung
2019-11-23
1
-2
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+3
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Conditioning abc9 on POs not accurate due to cells
Eddie Hung
2019-11-23
1
-15
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+6
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Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung
2019-11-23
1
-13
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+27
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Print ".en=" only if there is an enable signal
Eddie Hung
2019-11-23
1
-1
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+1
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Escape IdStrings
Eddie Hung
2019-11-23
1
-3
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+2
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More sane naming of submod
Eddie Hung
2019-11-23
1
-2
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+2
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Add -set_attr option, -unpart to take attr name
Eddie Hung
2019-11-23
1
-10
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+25
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Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung
2019-11-23
1
-18
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+34
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Do not use log_signal() for empty SigSpec to prevent "{ }"
Eddie Hung
2019-11-22
1
-2
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+4
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Call submod once, more meaningful submod names, ignore largest domain
Eddie Hung
2019-11-22
1
-18
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+32
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Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung
2019-11-22
3
-1
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+1
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Move clkpart into passes/hierarchy
Eddie Hung
2019-11-22
3
-1
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+1
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-22
1
-48
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+39
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submod to bitty rather bussy, for bussy wires used as input and output
Eddie Hung
2019-11-22
1
-48
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+39
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-22
1
-2
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+10
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Constant driven signals are also an input to submodules
Eddie Hung
2019-11-22
1
-2
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+10
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-22
1
-1
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+0
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Oops
Eddie Hung
2019-11-22
1
-1
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+0
*
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Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung
2019-11-22
1
-8
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+9
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Only action if there is more than one clock domain
Eddie Hung
2019-11-22
1
-7
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+8
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Replace TODO
Eddie Hung
2019-11-22
1
-1
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+1
*
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Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung
2019-11-22
1
-1
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+19
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sigmap(wire) should inherit port_output status of POs
Eddie Hung
2019-11-22
1
-1
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+19
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Merge branch 'eddie/clkpart' into xaig_dff
Eddie Hung
2019-11-22
2
-1
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+2
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Brackets
Eddie Hung
2019-11-22
1
-1
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+1
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Entry in Makefile.inc
Eddie Hung
2019-11-22
1
-0
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+1
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Merge branch 'eddie/clkpart' into xaig_dff
Eddie Hung
2019-11-22
5
-4
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+430
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New 'clkpart' to {,un}partition design according to clock/enable
Eddie Hung
2019-11-22
1
-0
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+268
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