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* Connections between inputs and inouts are driven by the inputClifford Wolf2016-04-261-0/+3
* Fixed test_autotb for modules with many cell portsClifford Wolf2016-04-251-3/+6
* Fixed proc_mux performance bugClifford Wolf2016-04-251-0/+3
* Fixed performance bug in proc_dlatchClifford Wolf2016-04-241-2/+61
* Improvements in greenpak4 shreg mappingClifford Wolf2016-04-231-16/+35
* Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-04-231-0/+1
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| * Added "shregmap -zinit" for greenpak4 techClifford Wolf2016-04-231-0/+1
* | Fixed typo in help textAndrew Zonenberg2016-04-221-1/+1
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* Added "shregmap -tech greenpak4"Clifford Wolf2016-04-221-6/+97
* More flexible handling of initialization valuesClifford Wolf2016-04-221-7/+22
* Added "yosys -D" featureClifford Wolf2016-04-2180-102/+102
* Fixed performance bug in "share" passClifford Wolf2016-04-211-2/+51
* Improvements in opt_exprClifford Wolf2016-04-211-12/+62
* Bugfix and improvements in memory_shareClifford Wolf2016-04-211-22/+19
* Added "shregmap -params"Clifford Wolf2016-04-181-4/+43
* Added "shregmap -zinit" and "shregmap -init"Clifford Wolf2016-04-181-2/+65
* Improvements in "shregmap"Clifford Wolf2016-04-171-30/+140
* Added "shregmap" passClifford Wolf2016-04-162-0/+262
* Fixed copy&paste error in log message in lut2muxClifford Wolf2016-04-161-1/+1
* Prefer noninverting FFs in dfflibmapClifford Wolf2016-04-051-4/+20
* Improved formatting of "sat" output tablesClifford Wolf2016-04-051-5/+5
* Improved opt_merge support for $pmux cellsClifford Wolf2016-03-311-4/+46
* Preserve empty $pmux default casesClifford Wolf2016-03-311-2/+2
* Typo fixes in opt_expr and opt_mergeClifford Wolf2016-03-312-2/+2
* Renamed opt_share to opt_mergeClifford Wolf2016-03-314-19/+19
* Renamed opt_const to opt_exprClifford Wolf2016-03-314-56/+57
* Renamed counters pass to greenpak4_countersAndrew Zonenberg2016-03-302-286/+0
* Added initial implementation of "counters" pass to synth_greenpak4. Can only ...Andrew Zonenberg2016-03-301-25/+37
* Reduced log verbosityAndrew Zonenberg2016-03-301-9/+8
* Continued work on counter extraction. Can recognize compatible RTL counters b...Andrew Zonenberg2016-03-301-101/+155
* Merge https://github.com/cliffordwolf/yosysAndrew Zonenberg2016-03-301-2/+6
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| * Added support for installed pluginsClifford Wolf2016-03-301-2/+6
* | Fixed typo in log messageAndrew Zonenberg2016-03-301-1/+1
* | Initial work on greenpak4 counter extraction. Doesn't work but a decent startAndrew Zonenberg2016-03-302-0/+221
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* Fixed handling of inverters (aka 1-input luts) in nlutmapClifford Wolf2016-03-231-2/+2
* Cleanup abstract modules at end of "hierarchy -top"Clifford Wolf2016-03-211-2/+0
* Support for abstract modules in chparamClifford Wolf2016-03-211-0/+6
* Improvements in ABCEXTERNAL handlingClifford Wolf2016-03-192-8/+17
* Support calling out to an external ABC.Sergey Kvachonok2016-03-191-4/+8
* Using "mfs" and "lutpack" in ABC lut mappingClifford Wolf2016-03-071-5/+14
* Fixed some visual studio warningsClifford Wolf2016-02-132-2/+2
* Added "int ceil_log2(int)" functionClifford Wolf2016-02-131-1/+1
* Added "stat -liberty" for calculating chip areaClifford Wolf2016-02-041-6/+60
* Improved dffsr2dff passClifford Wolf2016-02-021-5/+50
* Added dffsr2dffClifford Wolf2016-02-022-0/+169
* Use alphanumerical order instead of idstring idx in opt_clean compare_signals()Clifford Wolf2016-02-021-1/+1
* Added "abc -luts" option, Improved Xilinx logic mappingClifford Wolf2016-02-011-13/+37
* Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)Clifford Wolf2016-02-011-8/+68
* More clang sanitizer stuffClifford Wolf2016-01-311-1/+1
* Added "equiv_struct -fwonly"Clifford Wolf2016-01-081-5/+17
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