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| author | Clifford Wolf <clifford@clifford.at> | 2016-04-25 10:43:04 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-04-25 10:43:04 +0200 |
| commit | 93e107e455b506731d9114e0dc2644f78797cf0f (patch) | |
| tree | add4b40ad49d65a3d962a7f40d4f320aff172133 /passes | |
| parent | d086224a39fcd488062d7f75cc936cce5435069c (diff) | |
| download | yosys-93e107e455b506731d9114e0dc2644f78797cf0f.tar.gz yosys-93e107e455b506731d9114e0dc2644f78797cf0f.tar.bz2 yosys-93e107e455b506731d9114e0dc2644f78797cf0f.zip | |
Fixed proc_mux performance bug
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/proc/proc_mux.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index dcfa212b5..e52c5556e 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -250,6 +250,9 @@ void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::ve log_assert(last_mux_cell != NULL); log_assert(when_signal.size() == last_mux_cell->getPort("\\A").size()); + if (when_signal == last_mux_cell->getPort("\\A")) + return; + RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw); log_assert(ctrl_sig.size() == 1); last_mux_cell->type = "$pmux"; |