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| author | Clifford Wolf <clifford@clifford.at> | 2016-04-26 19:49:05 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-04-26 19:49:05 +0200 |
| commit | 0d2923cccd00ed14537f3239b0059a76673798a4 (patch) | |
| tree | 9e30c2cf5b60b2aabfdbec1b7d8676c3734c9a56 /passes | |
| parent | 958fb29c76a13838a922ff8553178d2c31c1ddef (diff) | |
| download | yosys-0d2923cccd00ed14537f3239b0059a76673798a4.tar.gz yosys-0d2923cccd00ed14537f3239b0059a76673798a4.tar.bz2 yosys-0d2923cccd00ed14537f3239b0059a76673798a4.zip | |
Connections between inputs and inouts are driven by the input
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_clean.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 466808216..6600ffa25 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -156,6 +156,9 @@ bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool ®s, SigPoo if (w1->port_input != w2->port_input) return w2->port_input; + if ((w1->port_input && w1->port_output) != (w2->port_input && w2->port_output)) + return !(w2->port_input && w2->port_output); + if (w1->name[0] == '\\' && w2->name[0] == '\\') { if (regs.check_any(s1) != regs.check_any(s2)) return regs.check_any(s2); |