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Author
Age
Files
Lines
*
Do not call "setundef -zero" in abc9
Eddie Hung
2019-06-20
1
-5
/
+2
*
Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-06-20
8
-11
/
+51
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\
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*
Fix typo, fixes #1095
Clifford Wolf
2019-06-20
1
-1
/
+1
|
*
Improve shregmap help message, fixes #1113
Clifford Wolf
2019-06-20
1
-0
/
+2
|
*
Fix typo
Clifford Wolf
2019-06-20
1
-2
/
+2
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*
Fixed the help summary line for a few commands
acw1251
2019-06-19
3
-5
/
+5
|
*
Fix bug in #1078, add entry to CHANGELOG
Eddie Hung
2019-06-19
1
-3
/
+3
|
*
Use input default values in hierarchy pass
Clifford Wolf
2019-06-19
1
-0
/
+38
*
|
Remove iterator based Module::remove as per @cliffordwolf
Eddie Hung
2019-06-18
1
-7
/
+6
*
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&scorr before &sweep, remove &retime as recommended
Eddie Hung
2019-06-17
1
-1
/
+1
*
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Copy not move parameters/attributes
Eddie Hung
2019-06-17
1
-3
/
+4
*
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Fix leak removing cells during ABC integration; also preserve attr
Eddie Hung
2019-06-17
1
-25
/
+26
*
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Re-enable &dc2
Eddie Hung
2019-06-17
1
-1
/
+1
*
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Cleanup
Eddie Hung
2019-06-16
1
-51
/
+7
*
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Get rid of compiler warnings
Eddie Hung
2019-06-14
1
-5
/
+5
*
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Update abc9 -D doc
Eddie Hung
2019-06-14
1
-1
/
+2
*
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Enable "abc9 -D <num>" for timing-driven synthesis
Eddie Hung
2019-06-14
1
-9
/
+9
*
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Further cleanup based on @daveshah1
Eddie Hung
2019-06-14
1
-10
/
+0
*
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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung
2019-06-14
1
-0
/
+9
|
\
\
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*
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ecp5: Add abc9 option
David Shah
2019-06-14
1
-0
/
+9
*
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Remove extra semicolon
Eddie Hung
2019-06-14
1
-1
/
+1
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/
/
*
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Rip out all non FPGA stuff from abc9
Eddie Hung
2019-06-12
1
-343
/
+111
*
|
Fix spelling
Eddie Hung
2019-06-12
1
-1
/
+1
*
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Revert "For 'stat' do not count modules with abc_box_id"
Eddie Hung
2019-06-12
1
-3
/
+0
*
|
Be more precise when connecting during ABC9 re-integration
Eddie Hung
2019-06-12
1
-1
/
+3
*
|
Remove hacky wideports_split from abc9
Eddie Hung
2019-06-12
1
-52
/
+4
*
|
Fix compile errors when #if 1 for debug
Eddie Hung
2019-06-12
1
-7
/
+8
*
|
Do not call abc9 if no outputs
Eddie Hung
2019-06-12
1
-54
/
+65
*
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More write_xaiger cleanup
Eddie Hung
2019-06-12
1
-1
/
+1
*
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Consistency
Eddie Hung
2019-06-12
1
-1
/
+1
*
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Merge branch 'xc7mux' into xaig
Eddie Hung
2019-06-12
1
-1
/
+1
|
\
\
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*
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Typo: wire delay is -W argument
Eddie Hung
2019-06-12
1
-1
/
+1
*
|
|
Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7...
Eddie Hung
2019-06-12
1
-6
/
+3
*
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Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
Eddie Hung
2019-06-12
2
-267
/
+0
*
|
|
Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
Eddie Hung
2019-06-12
1
-14
/
+10
*
|
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Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"
Eddie Hung
2019-06-12
1
-5
/
+13
*
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Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"
Eddie Hung
2019-06-12
1
-13
/
+5
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/
/
*
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Add "-W' wire delay arg to abc9, use from synth_xilinx
Eddie Hung
2019-06-11
1
-5
/
+13
*
|
Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7...
Eddie Hung
2019-06-11
1
-15
/
+10
*
|
Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
Eddie Hung
2019-06-11
1
-10
/
+15
|
\
\
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*
|
Try way that doesn't involve creating a new wire
Eddie Hung
2019-06-11
1
-10
/
+15
*
|
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Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
Eddie Hung
2019-06-10
1
-3
/
+6
|
\
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*
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If d_bit already in sigbit_chain_next, create extra wire
Eddie Hung
2019-06-10
1
-3
/
+6
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/
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*
Allow muxcover costs to be changed
Eddie Hung
2019-06-07
1
-12
/
+42
*
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Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"
Eddie Hung
2019-06-10
1
-4
/
+4
*
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Revert "shregmap -tech xilinx_dynamic to work -params and -enpol"
Eddie Hung
2019-06-10
1
-26
/
+6
*
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Revert "Refactor to ShregmapTechXilinx7Static"
Eddie Hung
2019-06-10
1
-86
/
+46
*
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Revert "Add -tech xilinx_static"
Eddie Hung
2019-06-10
1
-13
/
+2
*
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Revert "Continue support for ShregmapTechXilinx7Static"
Eddie Hung
2019-06-10
1
-81
/
+30
*
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Revert "shregmap -tech xilinx_static to handle INIT"
Eddie Hung
2019-06-10
1
-32
/
+22
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