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authorEddie Hung <eddie@fpgeh.com>2019-06-18 12:47:12 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-18 12:47:12 -0700
commit7324a4c2cd0132f792f4fade1a77aeceae46bd85 (patch)
tree4510f12308d725eeeac2b2635cf73dc08823f80c /passes
parent6a4025b5eef3ea96a8a7cdb0046cb2193cfa08e5 (diff)
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Remove iterator based Module::remove as per @cliffordwolf
Diffstat (limited to 'passes')
-rw-r--r--passes/techmap/abc9.cc13
1 files changed, 6 insertions, 7 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 2f670dba2..7b13239f2 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -510,16 +510,15 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
vector<RTLIL::Cell*> boxes;
- for (auto it = module->cells_.begin(); it != module->cells_.end(); ) {
- RTLIL::Cell* cell = it->second;
+ for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it) {
+ RTLIL::Cell *cell = it->second;
if (cell->type.in("$_AND_", "$_NOT_", "$__ABC_FF_")) {
- it = module->remove(it);
+ module->remove(cell);
continue;
}
RTLIL::Module* box_module = design->module(cell->type);
if (box_module && box_module->attributes.count("\\abc_box_id"))
- boxes.emplace_back(it->second);
- ++it;
+ boxes.emplace_back(cell);
}
std::map<std::string, int> cell_stats;
@@ -620,8 +619,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
}
- for (auto cell : boxes)
- module->remove(cell);
+ for (auto cell : boxes)
+ module->remove(cell);
// Copy connections (and rename) from mapped_mod to module
for (auto conn : mapped_mod->connections()) {