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* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-1513-1000/+1000
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| * Merge remote-tracking branch 'origin/master' into eddie/fix_1284_againEddie Hung2019-08-1512-998/+998
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| | * Merge branch 'master' into clifford/idsClifford Wolf2019-08-151-1/+49
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| | * | Use ID() macro in all of passes/opt/Clifford Wolf2019-08-1112-998/+998
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was obtained by running the following SED command in passes/opt/ and then using "meld foo.cc foo.cc.orig" to manually fix all resulting compiler errors. sed -i.orig -r 's/"\\\\([a-zA-Z0-9_]+)"/ID(\1)/g; s/"(\$[a-zA-Z0-9_]+)"/ID(\1)/g;' *.cc Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | AND with an inverted input, causes X{,N}OR output to be inverted tooEddie Hung2019-08-141-2/+2
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| * | | Revert "Only sort leaves on non-ANDNOT/ORNOT cells"Eddie Hung2019-08-141-7/+6
| | | | | | | | | | | | | | | | This reverts commit 5ec5f6dec7d4cdcfd9e1a2cda999886605778400.
| * | | Only sort leaves on non-ANDNOT/ORNOT cellsEddie Hung2019-08-141-6/+7
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| * | Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves"Eddie Hung2019-08-141-4/+8
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| * | Since $_ANDNOT_ is not symmetric, do not sort leavesEddie Hung2019-08-121-8/+4
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* | | ffH -> ffFJKGEddie Hung2019-08-152-15/+15
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* | | Fixes for reverting SigSpec helper functionsEddie Hung2019-08-142-10/+14
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* | | Perform C -> PCIN optimisation after pattern matcherEddie Hung2019-08-132-19/+72
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* | | Revert changes to RTLIL::SigSpec methodsEddie Hung2019-08-132-7/+30
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* | | Rename to XilinxDspPassEddie Hung2019-08-131-3/+3
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* | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-1240-250/+334
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| * | Merge remote-tracking branch 'origin/master' into eddie/fix_1262Eddie Hung2019-08-1142-360/+279
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| | * Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-103-111/+0
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| | * Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-1038-225/+218
| | |\ | | | | | | | | Cleanup a few barnacles across codebase
| | | * substr() -> compare()Eddie Hung2019-08-0718-74/+74
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| | | * RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-077-48/+48
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| | | * Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-074-41/+54
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| | | * | Remove std:: namespaceEddie Hung2019-08-071-5/+5
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| | | * | stoi -> atoiEddie Hung2019-08-0734-110/+110
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| | | * | IdString::str().substr() -> IdString::substr()Eddie Hung2019-08-061-1/+1
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| | | * | Fix typosEddie Hung2019-08-061-5/+5
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| | | * | Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-0631-100/+100
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| | | * | Use IdString::begins_with()Eddie Hung2019-08-062-19/+17
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| | | * | Use State::S{0,1}Eddie Hung2019-08-066-12/+12
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| | | * | Make liberal use of IdString.in()Eddie Hung2019-08-0614-34/+34
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| | | * | Cleanup opt_expr.ccEddie Hung2019-08-061-35/+30
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| | * | | Merge pull request #1276 from YosysHQ/clifford/fix1273Clifford Wolf2019-08-101-15/+54
| | |\ \ \ | | | | | | | | | | | | Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib
| | | * | | Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib, add "abc -g ↵Clifford Wolf2019-08-091-15/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | all", fixes #1273 Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Merge pull request #1267 from whitequark/proc_prune-fix-1243whitequark2019-08-091-9/+7
| | |\ \ \ \ | | | |/ / / | | |/| | | proc_prune: fix handling of exactly identical assigns
| | | * | | proc_prune: fix handling of exactly identical assigns.whitequark2019-08-081-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, in a process like: process $proc$bug.v:8$3 assign $foo \bar switch \sel case 1'1 assign $foo 1'1 assign $foo 1'1 case assign $foo 1'0 end end both of the "assign $foo 1'1" would incorrectly be removed. Fixes #1243.
| * | | | | Wrong way aroundEddie Hung2019-08-101-2/+2
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| * | | | | cover_list -> cover as per @cliffordwolfEddie Hung2019-08-101-2/+2
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| * | | | | GrammarEddie Hung2019-08-091-1/+1
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| * | | | | Separate $alu handlingEddie Hung2019-08-091-7/+50
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| * | | | | opt_expr -fine to trim LSBs of $alu tooEddie Hung2019-08-091-4/+9
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| * | | | Merge pull request #1264 from YosysHQ/eddie/fix_1254Eddie Hung2019-08-081-0/+6
| |\ \ \ \ | | | | | | | | | | | | opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)
| | * | | | opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)Eddie Hung2019-08-071-0/+6
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| * / / / Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPEREddie Hung2019-08-073-0/+111
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* | | | Check nusers of DSP output, not whole flopEddie Hung2019-08-091-1/+1
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* | | | Improve ice40_dsp for non-fully-32-bit addersEddie Hung2019-08-091-3/+8
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* | | | Another filter -> ifEddie Hung2019-08-091-2/+2
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* | | | CleanupEddie Hung2019-08-092-18/+18
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* | | | Pack partial-product adder DSP48E1 packingEddie Hung2019-08-092-10/+79
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* | | | Fix checkEddie Hung2019-08-091-4/+6
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* | | | Revert "Fix typo"Eddie Hung2019-08-091-1/+1
| | | | | | | | | | | | | | | | This reverts commit e3c39cc450a0317ad7e8234bb866d55465548c9c.
* | | | Remove muxY and ffY for nowEddie Hung2019-08-082-35/+33
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