RTLIL::S{0,1} -> State::S{0,1}

7 files changed, 48 insertions, 48 deletions

diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index 6095eaf30..a85c3bec0 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -168,7 +168,7 @@ undef_bit_in_next_state:
 			ctrl_in_bit_indices[ctrl_in[i]] = i;
 
 		for (auto &it : ctrl_in_bit_indices)
-			if (tr.ctrl_in.bits.at(it.second) == RTLIL::S1 && exclusive_ctrls.count(it.first) != 0)
+			if (tr.ctrl_in.bits.at(it.second) == State::S1 && exclusive_ctrls.count(it.first) != 0)
 				for (auto &dc_bit : exclusive_ctrls.at(it.first))
 					if (ctrl_in_bit_indices.count(dc_bit))
 						tr.ctrl_in.bits.at(ctrl_in_bit_indices.at(dc_bit)) = RTLIL::State::Sa;
@@ -216,13 +216,13 @@ undef_bit_in_next_state:
 		ce.push();
 		dont_care.append(undef);
 		ce.set(undef, constval.as_const());
-		if (exclusive_ctrls.count(undef) && constval == RTLIL::S1)
+		if (exclusive_ctrls.count(undef) && constval == State::S1)
 			for (auto &bit : exclusive_ctrls.at(undef)) {
 				RTLIL::SigSpec bitval = bit;
-				if (ce.eval(bitval) && bitval != RTLIL::S0)
+				if (ce.eval(bitval) && bitval != State::S0)
 					goto found_contradiction_1;
 				else
-					ce.set(bit, RTLIL::S0);
+					ce.set(bit, State::S0);
 			}
 		find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care);
 	found_contradiction_1:
@@ -231,21 +231,21 @@ undef_bit_in_next_state:
 	else
 	{
 		ce.push(), ce_nostop.push();
-		ce.set(undef, RTLIL::S0);
-		ce_nostop.set(undef, RTLIL::S0);
+		ce.set(undef, State::S0);
+		ce_nostop.set(undef, State::S0);
 		find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care);
 		ce.pop(), ce_nostop.pop();
 
 		ce.push(), ce_nostop.push();
-		ce.set(undef, RTLIL::S1);
-		ce_nostop.set(undef, RTLIL::S1);
+		ce.set(undef, State::S1);
+		ce_nostop.set(undef, State::S1);
 		if (exclusive_ctrls.count(undef))
 			for (auto &bit : exclusive_ctrls.at(undef)) {
 				RTLIL::SigSpec bitval = bit;
-				if ((ce.eval(bitval) || ce_nostop.eval(bitval)) && bitval != RTLIL::S0)
+				if ((ce.eval(bitval) || ce_nostop.eval(bitval)) && bitval != State::S0)
 					goto found_contradiction_2;
 				else
-					ce.set(bit, RTLIL::S0), ce_nostop.set(bit, RTLIL::S0);
+					ce.set(bit, State::S0), ce_nostop.set(bit, RTLIL::S0);
 			}
 		find_transitions(ce, ce_nostop, fsm_data, states, state_in, ctrl_in, ctrl_out, dff_in, dont_care);
 	found_contradiction_2:
@@ -263,8 +263,8 @@ static void extract_fsm(RTLIL::Wire *wire)
 	RTLIL::SigSpec dff_in(RTLIL::State::Sm, wire->width);
 	RTLIL::Const reset_state(RTLIL::State::Sx, wire->width);
 
-	RTLIL::SigSpec clk = RTLIL::S0;
-	RTLIL::SigSpec arst = RTLIL::S0;
+	RTLIL::SigSpec clk = State::S0;
+	RTLIL::SigSpec arst = State::S0;
 	bool clk_polarity = true;
 	bool arst_polarity = true;
 
@@ -371,8 +371,8 @@ static void extract_fsm(RTLIL::Wire *wire)
 	RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), "$fsm");
 	fsm_cell->setPort("\\CLK", clk);
 	fsm_cell->setPort("\\ARST", arst);
-	fsm_cell->parameters["\\CLK_POLARITY"] = clk_polarity ? RTLIL::S1 : RTLIL::S0;
-	fsm_cell->parameters["\\ARST_POLARITY"] = arst_polarity ? RTLIL::S1 : RTLIL::S0;
+	fsm_cell->parameters["\\CLK_POLARITY"] = clk_polarity ? State::S1 : State::S0;
+	fsm_cell->parameters["\\ARST_POLARITY"] = arst_polarity ? State::S1 : State::S0;
 	fsm_cell->setPort("\\CTRL_IN", ctrl_in);
 	fsm_cell->setPort("\\CTRL_OUT", ctrl_out);
 	fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name.str());
diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index 6697d6ca1..225c30d9a 100644
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -49,7 +49,7 @@ struct ExclusiveDatabase
 			}
 			else if (cell->type == "$logic_not") {
 				nonconst_sig = sigmap(cell->getPort("\\A"));
-				const_sig = Const(RTLIL::S0, GetSize(nonconst_sig));
+				const_sig = Const(State::S0, GetSize(nonconst_sig));
 				y_port = sigmap(cell->getPort("\\Y"));
 			}
 			else if (cell->type == "$reduce_or") {
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 34919cf07..31c1d6f80 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -593,7 +593,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 					c->setPort("\\Y", module->addWire(NEW_ID));
 					RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
 					log_assert(wire);
-					module->connect(RTLIL::SigBit(wire, y_bit.offset), RTLIL::S1);
+					module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
 				}
 				else if (!lut_costs.empty() || !lut_file.empty()) {
 					RTLIL::Cell* driver_lut = nullptr;
diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index dc7d416b0..5c9e42fd4 100644
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -315,7 +315,7 @@ struct AlumaccWorker
 			}
 
 			if (subtract_b)
-				C.append(RTLIL::S1);
+				C.append(State::S1);
 
 			if (GetSize(C) > 1)
 				goto next_macc;
@@ -402,7 +402,7 @@ struct AlumaccWorker
 			alunode_t *n = nullptr;
 
 			for (auto node : sig_alu[RTLIL::SigSig(A, B)])
-				if (node->is_signed == is_signed && node->invert_b && node->c == RTLIL::S1) {
+				if (node->is_signed == is_signed && node->invert_b && node->c == State::S1) {
 					n = node;
 					break;
 				}
@@ -411,7 +411,7 @@ struct AlumaccWorker
 				n = new alunode_t;
 				n->a = A;
 				n->b = B;
-				n->c = RTLIL::S1;
+				n->c = State::S1;
 				n->y = module->addWire(NEW_ID, max(GetSize(A), GetSize(B)));
 				n->is_signed = is_signed;
 				n->invert_b = true;
@@ -440,7 +440,7 @@ struct AlumaccWorker
 			alunode_t *n = nullptr;
 
 			for (auto node : sig_alu[RTLIL::SigSig(A, B)])
-				if (node->is_signed == is_signed && node->invert_b && node->c == RTLIL::S1) {
+				if (node->is_signed == is_signed && node->invert_b && node->c == State::S1) {
 					n = node;
 					break;
 				}
@@ -484,8 +484,8 @@ struct AlumaccWorker
 
 			n->alu_cell->setPort("\\A", n->a);
 			n->alu_cell->setPort("\\B", n->b);
-			n->alu_cell->setPort("\\CI", GetSize(n->c) ? n->c : RTLIL::S0);
-			n->alu_cell->setPort("\\BI", n->invert_b ? RTLIL::S1 : RTLIL::S0);
+			n->alu_cell->setPort("\\CI", GetSize(n->c) ? n->c : State::S0);
+			n->alu_cell->setPort("\\BI", n->invert_b ? State::S1 : State::S0);
 			n->alu_cell->setPort("\\Y", n->y);
 			n->alu_cell->setPort("\\X", module->addWire(NEW_ID, GetSize(n->y)));
 			n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, GetSize(n->y)));
diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index 8e947b4dc..2dc577c73 100644
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -167,7 +167,7 @@ struct Dff2dffeWorker
 		}
 
 		if (GetSize(or_input) == 0)
-			return RTLIL::S1;
+			return State::S1;
 
 		if (GetSize(or_input) == 1)
 			return or_input;
diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc
index 3e8e59e6b..59e58e4db 100644
--- a/passes/techmap/maccmap.cc
+++ b/passes/techmap/maccmap.cc
@@ -36,7 +36,7 @@ struct MaccmapWorker
 
 	void add(RTLIL::SigBit bit, int position)
 	{
-		if (position >= width || bit == RTLIL::S0)
+		if (position >= width || bit == State::S0)
 			return;
 
 		if (bits.at(position).count(bit)) {
@@ -53,7 +53,7 @@ struct MaccmapWorker
 
 		if (do_subtract) {
 			a = module->Not(NEW_ID, a);
-			add(RTLIL::S1, 0);
+			add(State::S1, 0);
 		}
 
 		for (int i = 0; i < width; i++)
@@ -80,7 +80,7 @@ struct MaccmapWorker
 			else
 			{
 				add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
-				a = {a.extract(0, width-1), RTLIL::S0};
+				a = {a.extract(0, width-1), State::S0};
 			}
 	}
 
@@ -88,10 +88,10 @@ struct MaccmapWorker
 	{
 		int start_index = 0, stop_index = GetSize(in1);
 
-		while (start_index < stop_index && in1[start_index] == RTLIL::S0 && in2[start_index] == RTLIL::S0 && in3[start_index] == RTLIL::S0)
+		while (start_index < stop_index && in1[start_index] == State::S0 && in2[start_index] == RTLIL::S0 && in3[start_index] == RTLIL::S0)
 			start_index++;
 
-		while (start_index < stop_index && in1[stop_index-1] == RTLIL::S0 && in2[stop_index-1] == RTLIL::S0 && in3[stop_index-1] == RTLIL::S0)
+		while (start_index < stop_index && in1[stop_index-1] == State::S0 && in2[stop_index-1] == RTLIL::S0 && in3[stop_index-1] == RTLIL::S0)
 			stop_index--;
 
 		if (start_index == stop_index)
@@ -222,7 +222,7 @@ struct MaccmapWorker
 					RTLIL::SigSpec in3 = summands[i+2];
 					RTLIL::SigSpec out1, out2;
 					fulladd(in1, in2, in3, out1, out2);
-					RTLIL::SigBit extra_bit = RTLIL::S0;
+					RTLIL::SigBit extra_bit = State::S0;
 					if (!tree_sum_bits.empty()) {
 						extra_bit = tree_sum_bits.back();
 						tree_sum_bits.pop_back();
@@ -240,8 +240,8 @@ struct MaccmapWorker
 		RTLIL::Cell *c = module->addCell(NEW_ID, "$alu");
 		c->setPort("\\A", summands.front());
 		c->setPort("\\B", summands.back());
-		c->setPort("\\CI", RTLIL::S0);
-		c->setPort("\\BI", RTLIL::S0);
+		c->setPort("\\CI", State::S0);
+		c->setPort("\\BI", State::S0);
 		c->setPort("\\Y", module->addWire(NEW_ID, width));
 		c->setPort("\\X", module->addWire(NEW_ID, width));
 		c->setPort("\\CO", module->addWire(NEW_ID, width));
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index e360b5edb..cea247dc7 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -186,7 +186,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 
 		RTLIL::SigSpec config;
 		for (int i = 0; i < (1 << width); i++)
-			config.append(xorshift32(2) ? RTLIL::S1 : RTLIL::S0);
+			config.append(xorshift32(2) ? State::S1 : State::S0);
 
 		cell->setParam("\\LUT", config.as_const());
 	}
@@ -209,16 +209,16 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 		for (int i = 0; i < width*depth; i++)
 			switch (xorshift32(3)) {
 				case 0:
-					config.append(RTLIL::S1);
-					config.append(RTLIL::S0);
+					config.append(State::S1);
+					config.append(State::S0);
 					break;
 				case 1:
-					config.append(RTLIL::S0);
-					config.append(RTLIL::S1);
+					config.append(State::S0);
+					config.append(State::S1);
 					break;
 				case 2:
-					config.append(RTLIL::S0);
-					config.append(RTLIL::S0);
+					config.append(State::S0);
+					config.append(State::S0);
 					break;
 			}
 
@@ -308,18 +308,18 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
 			case 0:
 				n = xorshift32(GetSize(sig) + 1);
 				for (int i = 0; i < n; i++)
-					sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0;
+					sig[i] = xorshift32(2) == 1 ? State::S1 : State::S0;
 				break;
 			case 1:
 				n = xorshift32(GetSize(sig) + 1);
 				for (int i = n; i < GetSize(sig); i++)
-					sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0;
+					sig[i] = xorshift32(2) == 1 ? State::S1 : State::S0;
 				break;
 			case 2:
 				n = xorshift32(GetSize(sig));
 				m = xorshift32(GetSize(sig));
 				for (int i = min(n, m); i < max(n, m); i++)
-					sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0;
+					sig[i] = xorshift32(2) == 1 ? State::S1 : State::S0;
 				break;
 			}
 
@@ -491,7 +491,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
 
 			RTLIL::Const in_value;
 			for (int i = 0; i < GetSize(gold_wire); i++)
-				in_value.bits.push_back(xorshift32(2) ? RTLIL::S1 : RTLIL::S0);
+				in_value.bits.push_back(xorshift32(2) ? State::S1 : State::S0);
 
 			if (xorshift32(4) == 0) {
 				int inv_chance = 1 + xorshift32(8);
@@ -591,11 +591,11 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
 			}
 
 			for (int i = 0; i < GetSize(out_sig); i++) {
-				if (out_val[i] != RTLIL::S0 && out_val[i] != RTLIL::S1)
+				if (out_val[i] != State::S0 && out_val[i] != State::S1)
 					continue;
-				if (out_val[i] == RTLIL::S0 && sat1_model_value.at(i) == false)
+				if (out_val[i] == State::S0 && sat1_model_value.at(i) == false)
 					continue;
-				if (out_val[i] == RTLIL::S1 && sat1_model_value.at(i) == true)
+				if (out_val[i] == State::S1 && sat1_model_value.at(i) == true)
 					continue;
 				log_error("Mismatch in sat model 1 (no undef modeling) output!\n");
 			}
@@ -627,12 +627,12 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
 
 			for (int i = 0; i < GetSize(out_sig); i++) {
 				if (sat2_model_value.at(GetSize(out_sig) + i)) {
-					if (out_val[i] != RTLIL::S0 && out_val[i] != RTLIL::S1)
+					if (out_val[i] != State::S0 && out_val[i] != State::S1)
 						continue;
 				} else {
-					if (out_val[i] == RTLIL::S0 && sat2_model_value.at(i) == false)
+					if (out_val[i] == State::S0 && sat2_model_value.at(i) == false)
 						continue;
-					if (out_val[i] == RTLIL::S1 && sat2_model_value.at(i) == true)
+					if (out_val[i] == State::S1 && sat2_model_value.at(i) == true)
 						continue;
 				}
 				log_error("Mismatch in sat model 2 (undef modeling) output!\n");