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* Merge $macc cells in alumacc passClifford Wolf2014-09-141-1/+59
* Basic $macc extract in alumaccClifford Wolf2014-09-141-4/+104
* alumacc skeletonClifford Wolf2014-09-142-0/+64
* Cleanup in wreduceClifford Wolf2014-09-141-11/+8
* Added $lcu cell typeClifford Wolf2014-09-081-1/+26
* Added "$fa" cell typeClifford Wolf2014-09-082-6/+47
* Trim msb/lsb zero bits from full adder in maccmapClifford Wolf2014-09-081-5/+27
* Added "test_cell -const"Clifford Wolf2014-09-081-2/+45
* Added 'techmap_maccmap' techmap attributeClifford Wolf2014-09-071-19/+53
* Added "maccmap" commandClifford Wolf2014-09-072-0/+319
* Added "test_cell -nosat"Clifford Wolf2014-09-071-59/+73
* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-061-1/+1
* Added $macc SAT modelClifford Wolf2014-09-061-5/+6
* Added $macc cell typeClifford Wolf2014-09-061-2/+53
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-09-069-15/+15
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| * Corrected spelling mistakes found by lintianRuben Undheim2014-09-069-15/+15
* | Added "test_cell -script"Clifford Wolf2014-09-061-1/+8
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* Fixed "opt_const -fine" for $pos cellsClifford Wolf2014-09-041-9/+4
* Removed $bu0 cell typeClifford Wolf2014-09-046-24/+9
* Fixed "test_cells -vlog"Clifford Wolf2014-09-031-4/+6
* Improvements in "test_cell -vlog"Clifford Wolf2014-09-021-3/+8
* Added test_cell -vlogClifford Wolf2014-09-021-2/+79
* Added SAT testing to test_cell eval stageClifford Wolf2014-09-021-1/+89
* Removed references to yosys-svgviewer from docsClifford Wolf2014-09-021-2/+2
* Using "xdot" instead of "yosys-svgviewer" in show commandClifford Wolf2014-09-021-4/+3
* Added $alu support to test_cellClifford Wolf2014-09-011-1/+22
* Added "test_cell -simlib -v"Clifford Wolf2014-09-011-8/+29
* Added "techmap -autoproc"Clifford Wolf2014-09-011-2/+18
* Fixes in old SAT example.ysClifford Wolf2014-09-011-3/+4
* Moved "share" and "wreduce" to passes/opt/Clifford Wolf2014-09-015-2/+2
* Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-011-1/+1
* Added eval testing to test_cellClifford Wolf2014-08-311-0/+88
* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-311-5/+28
* Added design->scratchpadClifford Wolf2014-08-308-64/+19
* Improved write address decoder generation memory_mapClifford Wolf2014-08-301-16/+28
* Using worker class in memory_mapClifford Wolf2014-08-301-226/+231
* Don't change existing binary FSM encoding if it is already optimalClifford Wolf2014-08-301-1/+6
* Using $pmux info in fsm_extract to optimize transition ctrl_in patternsClifford Wolf2014-08-301-0/+10
* Improved handling of $pmux cells in fsm_extractClifford Wolf2014-08-301-20/+75
* Fixed inserting of Q-inverters in dfflibmapClifford Wolf2014-08-271-0/+5
* Implemented "rename -enumerate -pattern"Clifford Wolf2014-08-261-4/+13
* Optimize shift ops with constant rhs in opt_constClifford Wolf2014-08-241-0/+35
* Added some additional log messages to opt_constClifford Wolf2014-08-241-1/+10
* azonenberg: Make dump_vcd save model when temporal induction fails due to ste...Clifford Wolf2014-08-241-0/+2
* Only call proc_share_dirname() in techmap when necessaryClifford Wolf2014-08-231-2/+1
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-237-38/+47
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-232-97/+98
* Added "stat -width"Clifford Wolf2014-08-221-4/+37
* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-222-2/+16
* Added "plugin" commandClifford Wolf2014-08-222-0/+118
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