aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* Merge $macc cells in alumacc passClifford Wolf2014-09-141-1/+59
* Basic $macc extract in alumaccClifford Wolf2014-09-141-4/+104
* alumacc skeletonClifford Wolf2014-09-142-0/+64
* Cleanup in wreduceClifford Wolf2014-09-141-11/+8
* Using pkg-config to find libffiClifford Wolf2014-09-131-2/+2
* Fixed simlib $macc model for xilinx xsimClifford Wolf2014-09-081-1/+15
* Simplified $fa undef modelClifford Wolf2014-09-083-15/+6
* Fixes and cleanups for blackbox.vClifford Wolf2014-09-082-70/+73
* Added $lcu cell typeClifford Wolf2014-09-088-76/+142
* Another $clog2 bugfixClifford Wolf2014-09-081-0/+2
* Added "$fa" cell typeClifford Wolf2014-09-088-6/+165
* Trim msb/lsb zero bits from full adder in maccmapClifford Wolf2014-09-081-5/+27
* Added "test_cell -const"Clifford Wolf2014-09-081-2/+45
* Using maccmap for $macc and $mul techmapClifford Wolf2014-09-071-190/+16
* Added 'techmap_maccmap' techmap attributeClifford Wolf2014-09-071-19/+53
* Added "maccmap" commandClifford Wolf2014-09-072-0/+319
* Added "test_cell -nosat"Clifford Wolf2014-09-071-59/+73
* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-064-4/+5
* Added $macc eval modelClifford Wolf2014-09-061-0/+22
* Added $macc SAT modelClifford Wolf2014-09-064-11/+83
* Fixed $clog2 (off by one error)Clifford Wolf2014-09-061-2/+2
* Added $macc simlib model (also use as techmap rule for now)Clifford Wolf2014-09-062-0/+172
* Fixed assignment of out-of bounds array elementClifford Wolf2014-09-061-2/+26
* Added $macc cell typeClifford Wolf2014-09-064-9/+242
* Fixed autotest for non-basename argumentsClifford Wolf2014-09-061-0/+3
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-09-0625-39/+107
|\
| * Merge pull request #38 from rubund/masterClifford Wolf2014-09-0622-39/+39
| |\
| | * Corrected spelling mistakes found by lintianRuben Undheim2014-09-0622-39/+39
| |/
| * Added tests/various/constmsk_test.ysClifford Wolf2014-09-043-0/+68
* | Added "test_cell -script"Clifford Wolf2014-09-061-1/+8
|/
* Fixed "opt_const -fine" for $pos cellsClifford Wolf2014-09-041-9/+4
* Removed $bu0 cell typeClifford Wolf2014-09-0418-103/+27
* Using $pos models for $bu0Clifford Wolf2014-09-033-18/+3
* Fixed "test_cells -vlog"Clifford Wolf2014-09-031-4/+6
* Fixes in $alu SAT- and eval-modelsClifford Wolf2014-09-032-6/+5
* Undef-related fixes in simlib $alu modelClifford Wolf2014-09-021-3/+6
* Improvements in "test_cell -vlog"Clifford Wolf2014-09-021-3/+8
* Added test_cell -vlogClifford Wolf2014-09-021-2/+79
* Create a default selection stack in RTLIL::Design::Design()Clifford Wolf2014-09-022-2/+1
* Small bug fixes in $not, $neg, and $shiftx modelsClifford Wolf2014-09-023-9/+8
* Added SAT testing to test_cell eval stageClifford Wolf2014-09-021-1/+89
* Removed references to yosys-svgviewer from docsClifford Wolf2014-09-024-24/+12
* Removed yosys-svgviewerClifford Wolf2014-09-0214-1121/+18
* Using "xdot" instead of "yosys-svgviewer" in show commandClifford Wolf2014-09-022-5/+4
* Added $alu support to test_cellClifford Wolf2014-09-011-1/+22
* Added ConstEval model for $alu cellsClifford Wolf2014-09-011-0/+56
* Added SAT model for $alu cellsClifford Wolf2014-09-011-2/+69
* Fixed "test_cell -simlib all"Clifford Wolf2014-09-011-2/+3
* Added "test_cell -simlib -v"Clifford Wolf2014-09-011-8/+29
* Added "techmap -autoproc"Clifford Wolf2014-09-011-2/+18
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 16:07:44 +0000