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authorClifford Wolf <clifford@clifford.at>2014-09-08 12:15:39 +0200
committerClifford Wolf <clifford@clifford.at>2014-09-08 12:15:39 +0200
commitd46bac330520f91ee5bf8027abe98a8f9389f696 (patch)
treed1b87a2409d082fa281d2c9ea100e94c69a43912 /passes
parent1a88e47396305bd6b5ee2a7a91a1d014ebd37c10 (diff)
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Added "$fa" cell type
Diffstat (limited to 'passes')
-rw-r--r--passes/techmap/maccmap.cc22
-rw-r--r--passes/tests/test_cell.cc31
2 files changed, 47 insertions, 6 deletions
diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc
index a9c223fa8..c2dc9aa8a 100644
--- a/passes/techmap/maccmap.cc
+++ b/passes/techmap/maccmap.cc
@@ -106,12 +106,20 @@ struct MaccmapWorker
in2 = in2.extract(start_index, stop_index-start_index);
in3 = in3.extract(start_index, stop_index-start_index);
- RTLIL::SigSpec t1 = module->Xor(NEW_ID, in1, in2);
- out1 = {out_zeros_msb, module->Xor(NEW_ID, t1, in3), out_zeros_lsb};
-
- RTLIL::SigSpec t2 = module->And(NEW_ID, in1, in2);
- RTLIL::SigSpec t3 = module->And(NEW_ID, in3, t1);
- out2 = {out_zeros_msb, module->Or(NEW_ID, t2, t3), out_zeros_lsb};
+ int width = SIZE(in1);
+ RTLIL::Wire *w1 = module->addWire(NEW_ID, width);
+ RTLIL::Wire *w2 = module->addWire(NEW_ID, width);
+
+ RTLIL::Cell *cell = module->addCell(NEW_ID, "$fa");
+ cell->setParam("\\WIDTH", width);
+ cell->setPort("\\A", in1);
+ cell->setPort("\\B", in2);
+ cell->setPort("\\C", in3);
+ cell->setPort("\\Y", w1);
+ cell->setPort("\\X", w2);
+
+ out1 = {out_zeros_msb, w1, out_zeros_lsb};
+ out2 = {out_zeros_msb, w2, out_zeros_lsb};
}
}
@@ -198,6 +206,8 @@ struct MaccmapWorker
summands.swap(new_summands);
}
+ log_assert(tree_sum_bits.empty());
+
return module->Add(NEW_ID, summands.front(), summands.back());
}
};
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 310c3bdfe..72fb74d3a 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -39,6 +39,36 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
RTLIL::Cell *cell = module->addCell("\\UUT", cell_type);
RTLIL::Wire *wire;
+ if (cell_type == "$fa")
+ {
+ int width = 1 + xorshift32(8);
+
+ wire = module->addWire("\\A");
+ wire->width = width;
+ wire->port_input = true;
+ cell->setPort("\\A", wire);
+
+ wire = module->addWire("\\B");
+ wire->width = width;
+ wire->port_input = true;
+ cell->setPort("\\B", wire);
+
+ wire = module->addWire("\\C");
+ wire->width = width;
+ wire->port_input = true;
+ cell->setPort("\\C", wire);
+
+ wire = module->addWire("\\X");
+ wire->width = width;
+ wire->port_output = true;
+ cell->setPort("\\X", wire);
+
+ wire = module->addWire("\\Y");
+ wire->width = width;
+ wire->port_output = true;
+ cell->setPort("\\Y", wire);
+ }
+
if (cell_type == "$macc")
{
Macc macc;
@@ -603,6 +633,7 @@ struct TestCellPass : public Pass {
cell_types["$lut"] = "*";
cell_types["$alu"] = "ABSY";
cell_types["$macc"] = "*";
+ cell_types["$fa"] = "*";
for (; argidx < SIZE(args); argidx++)
{