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* Merge pull request #1767 from YosysHQ/eddie/idstringsEddie Hung2020-04-02114-2708/+2691
|\ | | | | IdString: use more ID::*, make them easier to use, speed up IdString::in()
| * kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-02109-2335/+2316
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| * kernel: use more ID::*Eddie Hung2020-04-0243-391/+393
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* | iopadmap: Fix z assignment to inout portMarcin Kościelnicki2020-04-021-1/+15
| | | | | | | | Fixes #1841.
* | Merge pull request #1842 from YosysHQ/mwk/fix-deminout-xzClaire Wolf2020-04-021-1/+1
|\ \ | |/ |/| deminout: prevent any constant assignment from demoting to input
| * deminout: prevent any constant assignment from demoting to inputMarcin Kościelnicki2020-03-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this patch, ``` module top(inout io); assign io = 1'bx; endmodule ``` would have the `io` pin demoted to input (same happens for `1'bz`, but not for `1'b0` or `1'b1`), resulting in check failures later on. Part of fix for #1841.
* | Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-0213-45/+45
|\ \ | | | | | | kernel: speedup by using more pass-by-const-ref
| * | kernel: more pass by const ref, more speedupsEddie Hung2020-03-181-1/+1
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| * | kernel: SigSpec use more const& + overloads to prevent implicit SigSpecEddie Hung2020-03-1312-44/+44
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* | | Merge pull request #1828 from YosysHQ/eddie/celltypes_speedupEddie Hung2020-04-013-21/+47
|\ \ \ | | | | | | | | kernel: share a single CellTypes within a pass
| * | | memory_share: fix stray braceEddie Hung2020-03-301-1/+0
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| * | | Code review fixesEddie Hung2020-03-302-3/+3
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| * | | Apply suggestions from code reviewEddie Hung2020-03-302-6/+2
| | | | | | | | | | | | Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
| * | | kernel: clear some more ShareWorker stateEddie Hung2020-03-261-0/+4
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| * | | kernel: share a single CellTypes within a passEddie Hung2020-03-183-21/+48
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* | | Merge pull request #1790 from YosysHQ/eddie/opt_expr_xorEddie Hung2020-04-011-3/+37
|\ \ \ | | | | | | | | opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs
| * | | opt_expr: fix failing $xnor testEddie Hung2020-03-201-2/+17
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| * | | opt_expr: fix missing braceEddie Hung2020-03-201-2/+4
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| * | | opt_expr: extend to $xnor and $_XNOR_Eddie Hung2020-03-191-8/+12
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| * | | opt_expr: optimise 1-bit $xor or $_XOR_ with constant inputEddie Hung2020-03-191-1/+14
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* | | Merge pull request #1789 from YosysHQ/eddie/opt_expr_aluEddie Hung2020-04-011-19/+51
|\ \ \ | | | | | | | | opt_expr: improve performance on $alu and $sub
| * | | opt_expr: remove redundantEddie Hung2020-03-191-3/+0
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| * | | opt_expr: optimise $sub when both A[i] and B[i] == 1'b1Eddie Hung2020-03-191-9/+20
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| * | | opt_expr: optimise for identity $alu-s just like $add/$subEddie Hung2020-03-191-7/+31
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* | | Merge pull request #1761 from YosysHQ/eddie/opt_merge_speedupEddie Hung2020-03-311-132/+102
|\ \ \ | | | | | | | | opt_merge: speedup
| * | | opt_merge: unordered_map -> dict as per @cliffordwolf reviewEddie Hung2020-03-161-1/+1
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| * | | opt_merge: speedupEddie Hung2020-03-161-132/+102
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* | | Merge pull request #1835 from boqwxp/cleanup_sat_exposeEddie Hung2020-03-301-85/+66
|\ \ \ | | | | | | | | Clean up pseudo-private member usage in `passes/sat/expose.cc`.
| * | | Remove unused function parameter.Alberto Gonzalez2020-03-301-2/+2
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| * | | Simplify iterating over selected modules or cells.Alberto Gonzalez2020-03-301-16/+4
| | | | | | | | | | | | | | | | Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
| * | | Clean up more in `passes/sat/expose.cc`.Alberto Gonzalez2020-03-301-64/+59
| | | | | | | | | | | | | | | | Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
| * | | Clean up pseudo-private member usage in `passes/sat/expose.cc`.Alberto Gonzalez2020-03-281-11/+9
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* | | | Merge pull request #1832 from boqwxp/cleanup_passes_cmds_designEddie Hung2020-03-301-31/+33
|\ \ \ \ | | | | | | | | | | Clean up pseudo-private member usage in `passes/cmds/design.cc`.
| * | | | Replace `RTLIL::id2cstr()` with `log_id()`.Alberto Gonzalez2020-03-301-1/+1
| | | | | | | | | | | | | | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | | | Clean up pseudo-private member usage in `passes/cmds/design.cc`.Alberto Gonzalez2020-03-281-31/+33
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* | | | Merge pull request #1786 from boqwxp/hierarchycc_cleanupEddie Hung2020-03-301-69/+63
|\ \ \ \ | | | | | | | | | | Clean up pseudo-private member usage in `passes/hierarchy/hierarchy.cc`.
| * | | | Fix double deletion in `passes/hierarchy/hierarchy.cc`.Alberto Gonzalez2020-03-301-1/+0
| | | | | | | | | | | | | | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | | | Clean up pseudo-private member usage in `passes/hierarchy/hierarchy.cc`.Alberto Gonzalez2020-03-191-68/+63
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* | | | | Merge pull request #1831 from boqwxp/cleanup_sat_evalEddie Hung2020-03-301-46/+44
|\ \ \ \ \ | | | | | | | | | | | | Clean up pseudo-private member usage in `passes/sat/eval.cc`.
| * | | | | Further clean up `passes/sat/eval.cc`.Alberto Gonzalez2020-03-301-16/+15
| | | | | | | | | | | | | | | | | | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | | | | Clean up pseudo-private member usage in `passes/sat/eval.cc`.Alberto Gonzalez2020-03-281-35/+34
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* | | | | Merge pull request #1833 from boqwxp/cleanup_sat_freduceEddie Hung2020-03-301-15/+13
|\ \ \ \ \ | | | | | | | | | | | | Clean up pseudo-private member usage in `passes/sat/freduce.cc`.
| * | | | | Further clean up `passes/sat/freduce.cc`.Alberto Gonzalez2020-03-301-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | | | | Clean up pseudo-private member usage in `passes/sat/freduce.cc`.Alberto Gonzalez2020-03-281-13/+12
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* | | | | Merge pull request #1778 from rswarbrick/sv-definesN. Engelhardt2020-03-301-1/+2
|\ \ \ \ \ | |_|_|_|/ |/| | | | Add support for SystemVerilog-style `define to Verilog frontend
| * | | | Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-271-1/+2
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
* | | | Explicit include of csignalMiodrag Milanovic2020-03-281-0/+1
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* | | | windows - there are no stopping signalsMiodrag Milanovic2020-03-281-0/+1
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* | | Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fixClaire Wolf2020-03-261-1/+1
|\ \ \ | | | | | | | | techmap: Fix cell names with _TECHMAP_REPLACE_.*
| * | | techmap: Fix cell names with _TECHMAP_REPLACE_.*Marcin Kościelnicki2020-03-231-1/+1
| | | | | | | | | | | | | | | | Fixes #1804.
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